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adamkondraciukadamkondraciuk
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drivers: pwm: pwm_nrfx: minor fixes
Minor alignment and fix failing tests. Signed-off-by: Adam Kondraciuk <[email protected]>
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‎drivers/pwm/pwm_nrfx.c‎

Lines changed: 59 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ struct pwm_nrfx_data {
6464
uint8_t prescaler;
6565
bool stop_requested;
6666
#ifdef PWM_NRFX_USE_CLOCK_CONTROL
67-
bool clock_requested;
67+
bool clock_requested;
6868
#endif
6969
};
7070

@@ -73,16 +73,15 @@ struct pwm_nrfx_data {
7373
* workaround.
7474
*/
7575
#define _PWM_DATA_STRUCT_NAME_GET(inst) pwm_nrfx_##inst##_data
76-
#define _PWM_DATA_STRUCT_DECLARE(inst) static struct pwm_nrfx_data _PWM_DATA_STRUCT_NAME_GET(inst);
76+
#define _PWM_DATA_STRUCT_DECLARE(inst) static struct pwm_nrfx_data _PWM_DATA_STRUCT_NAME_GET(inst);
7777
DT_INST_FOREACH_STATUS_OKAY(_PWM_DATA_STRUCT_DECLARE);
7878

7979
/* Create an array of pointers to all active PWM instances to loop over them in an EGU interrupt
8080
* handler.
8181
*/
8282
#define _PWM_DATA_STRUCT_PWM_PTR_COMMA_GET(inst) &_PWM_DATA_STRUCT_NAME_GET(inst).pwm,
8383
static nrfx_pwm_t *pwm_instances[] = {
84-
DT_INST_FOREACH_STATUS_OKAY(_PWM_DATA_STRUCT_PWM_PTR_COMMA_GET)
85-
};
84+
DT_INST_FOREACH_STATUS_OKAY(_PWM_DATA_STRUCT_PWM_PTR_COMMA_GET)};
8685

8786
/* Define an interrupt handler for the EGU instance used by the workaround which calls
8887
* nrfx_pwm_nrf52_anomaly_109_handler for all active PWM instances.
@@ -95,9 +94,8 @@ void anomaly_109_egu_handler(void)
9594
}
9695

9796
#define ANOMALY_109_EGU_IRQ_CONNECT(idx) _EGU_IRQ_CONNECT(idx)
98-
#define _EGU_IRQ_CONNECT(idx) \
99-
IRQ_CONNECT(DT_IRQN(DT_NODELABEL(egu##idx)), \
100-
DT_IRQ(DT_NODELABEL(egu##idx), priority), \
97+
#define _EGU_IRQ_CONNECT(idx) \
98+
IRQ_CONNECT(DT_IRQN(DT_NODELABEL(egu##idx)), DT_IRQ(DT_NODELABEL(egu##idx), priority), \
10199
anomaly_109_egu_handler, 0, 0)
102100
#else
103101
#define ANOMALY_109_EGU_IRQ_CONNECT(idx)
@@ -167,10 +165,8 @@ static bool pwm_period_check_and_set(const struct device *dev,
167165
data->period_cycles = period_cycles;
168166
data->prescaler = prescaler;
169167

170-
nrf_pwm_configure(data->pwm.p_reg,
171-
data->prescaler,
172-
config->initial_config.count_mode,
173-
(uint16_t)countertop);
168+
nrf_pwm_configure(data->pwm.p_reg, data->prescaler,
169+
config->initial_config.count_mode, (uint16_t)countertop);
174170
return true;
175171
}
176172

@@ -195,8 +191,8 @@ static int stop_pwm(const struct device *dev)
195191
struct pwm_nrfx_data *data = dev->data;
196192

197193
/* Don't wait here for the peripheral to actually stop. Instead,
198-
* ensure it is stopped before starting the next playback.
199-
*/
194+
* ensure it is stopped before starting the next playback.
195+
*/
200196
nrfx_pwm_stop(&data->pwm, false);
201197

202198
#if PWM_NRFX_USE_CLOCK_CONTROL
@@ -253,9 +249,8 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
253249
/* Constantly active (duty 100%). */
254250
/* This value is always greater than or equal to COUNTERTOP. */
255251
compare_value = PWM_NRFX_CH_COMPARE_MASK;
256-
needs_pwm = pwm_is_fast(config) ||
257-
(IS_ENABLED(NRF_PWM_HAS_IDLEOUT) &&
258-
IS_ENABLED(CONFIG_PWM_NRFX_NO_GLITCH_DUTY_100));
252+
needs_pwm = pwm_is_fast(config) || (IS_ENABLED(NRF_PWM_HAS_IDLEOUT) &&
253+
IS_ENABLED(CONFIG_PWM_NRFX_NO_GLITCH_DUTY_100));
259254
} else {
260255
/* PWM generation needed. Check if the requested period matches
261256
* the one that is currently set, or the PWM peripheral can be
@@ -315,7 +310,7 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
315310
#if PWM_NRFX_USE_CLOCK_CONTROL
316311
if (data->clock_requested) {
317312
int ret = nrf_clock_control_release(config->clk_dev,
318-
&config->clk_spec);
313+
&config->clk_spec);
319314

320315
if (ret < 0) {
321316
LOG_ERR("Global HSFLL release failed: %d", ret);
@@ -355,8 +350,7 @@ static int pwm_nrfx_set_cycles(const struct device *dev, uint32_t channel,
355350
*/
356351
#if PWM_NRFX_USE_CLOCK_CONTROL
357352
if (config->clk_dev && !data->clock_requested) {
358-
int ret = nrf_clock_control_request_sync(config->clk_dev,
359-
&config->clk_spec,
353+
int ret = nrf_clock_control_request_sync(config->clk_dev, &config->clk_spec,
360354
K_FOREVER);
361355

362356
if (ret < 0) {
@@ -477,84 +471,80 @@ static int pwm_nrfx_init(const struct device *dev)
477471
return pm_device_driver_init(dev, pwm_nrfx_pm_action);
478472
}
479473

480-
#define PWM_MEM_REGION(inst) DT_PHANDLE(DT_DRV_INST(inst), memory_regions)
474+
#define PWM_MEM_REGION(inst) DT_PHANDLE(DT_DRV_INST(inst), memory_regions)
481475

482-
#define PWM_MEMORY_SECTION(inst) \
483-
COND_CODE_1(DT_NODE_HAS_PROP(inst, memory_regions), \
476+
#define PWM_MEMORY_SECTION(inst) \
477+
COND_CODE_1(DT_NODE_HAS_PROP(DT_DRV_INST(inst), memory_regions), \
484478
(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \
485479
PWM_MEM_REGION(inst)))))), \
486480
())
487481

488-
#define PWM_GET_MEM_ATTR(inst) \
489-
COND_CODE_1(DT_NODE_HAS_PROP(inst, memory_regions), \
482+
#define PWM_GET_MEM_ATTR(inst) \
483+
COND_CODE_1(DT_NODE_HAS_PROP(DT_DRV_INST(inst), memory_regions), \
490484
(DT_PROP_OR(PWM_MEM_REGION(inst), zephyr_memory_attr, 0)), (0))
491485

492486
/* Fast instances depend on the global HSFLL clock controller (as they need
493487
* to request the highest frequency from it to operate correctly), so they
494488
* must be initialized after that controller driver, hence the default PWM
495489
* initialization priority may be too early for them.
496490
*/
497-
#if defined(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY) && \
491+
#if defined(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY) && \
498492
CONFIG_PWM_INIT_PRIORITY < CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY
499-
#define PWM_INIT_PRIORITY(inst) \
493+
#define PWM_INIT_PRIORITY(inst) \
500494
COND_CODE_1(PWM_NRFX_IS_FAST(inst), \
501495
(UTIL_INC(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY)), \
502496
(CONFIG_PWM_INIT_PRIORITY))
503497
#else
504498
#define PWM_INIT_PRIORITY(inst) CONFIG_PWM_INIT_PRIORITY
505499
#endif
506500

507-
#define PWM_NRFX_DEFINE(inst) \
508-
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(DT_DRV_INST(inst)); \
509-
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(inst)); \
510-
static struct pwm_nrfx_data pwm_nrfx_##inst##_data = { \
511-
.pwm = NRFX_PWM_INSTANCE(DT_INST_REG_ADDR(inst)), \
512-
}; \
513-
static uint16_t pwm_##inst##_seq_values[NRF_PWM_CHANNEL_COUNT] \
514-
PWM_MEMORY_SECTION(inst); \
515-
PINCTRL_DT_INST_DEFINE(inst); \
516-
static const struct pwm_nrfx_config pwm_nrfx_##inst##_config = { \
517-
.initial_config = { \
518-
.skip_gpio_cfg = true, \
519-
.skip_psel_cfg = true, \
520-
.base_clock = NRF_PWM_CLK_1MHz, \
521-
.count_mode = (DT_INST_PROP(inst, center_aligned) \
522-
? NRF_PWM_MODE_UP_AND_DOWN \
523-
: NRF_PWM_MODE_UP), \
524-
.top_value = 1000, \
525-
.load_mode = NRF_PWM_LOAD_INDIVIDUAL, \
526-
.step_mode = NRF_PWM_STEP_TRIGGERED, \
527-
}, \
528-
.seq.values.p_raw = pwm_##inst##_seq_values, \
529-
.seq.length = NRF_PWM_CHANNEL_COUNT, \
530-
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
501+
#define PWM_NRFX_DEFINE(inst) \
502+
NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(DT_DRV_INST(inst)); \
503+
NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(inst)); \
504+
static struct pwm_nrfx_data pwm_nrfx_##inst##_data = { \
505+
.pwm = NRFX_PWM_INSTANCE(DT_INST_REG_ADDR(inst)), \
506+
}; \
507+
static uint16_t pwm_##inst##_seq_values[NRF_PWM_CHANNEL_COUNT] PWM_MEMORY_SECTION(inst); \
508+
PINCTRL_DT_INST_DEFINE(inst); \
509+
static const struct pwm_nrfx_config pwm_nrfx_##inst##_config = { \
510+
.initial_config = \
511+
{ \
512+
.skip_gpio_cfg = true, \
513+
.skip_psel_cfg = true, \
514+
.base_clock = NRF_PWM_CLK_1MHz, \
515+
.count_mode = (DT_INST_PROP(inst, center_aligned) \
516+
? NRF_PWM_MODE_UP_AND_DOWN \
517+
: NRF_PWM_MODE_UP), \
518+
.top_value = 1000, \
519+
.load_mode = NRF_PWM_LOAD_INDIVIDUAL, \
520+
.step_mode = NRF_PWM_STEP_TRIGGERED, \
521+
}, \
522+
.seq.values.p_raw = pwm_##inst##_seq_values, \
523+
.seq.length = NRF_PWM_CHANNEL_COUNT, \
524+
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
531525
.clock_freq = COND_CODE_1(DT_INST_CLOCKS_HAS_IDX(inst, 0), \
532526
(DT_PROP(DT_INST_CLOCKS_CTLR(inst), clock_frequency)), \
533-
(16ul * 1000ul * 1000ul)), \
534-
IF_ENABLED(CONFIG_DCACHE, \
535-
(.mem_attr = PWM_GET_MEM_ATTR(inst),)) \
536-
IF_ENABLED(PWM_NRFX_USE_CLOCK_CONTROL, \
527+
(16ul * 1000ul * 1000ul)), \
528+
IF_ENABLED(CONFIG_DCACHE, \
529+
(.mem_attr = PWM_GET_MEM_ATTR(inst),)) \
530+
IF_ENABLED(PWM_NRFX_USE_CLOCK_CONTROL, \
537531
(.clk_dev = PWM_NRFX_IS_FAST(inst) \
538532
? DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)) \
539533
: NULL, \
540534
.clk_spec = { \
541535
.frequency = \
542536
NRF_PERIPH_GET_FREQUENCY(DT_DRV_INST(inst)), \
543-
},)) \
544-
}; \
545-
static int pwm_nrfx_init##inst(const struct device *dev) \
546-
{ \
547-
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), \
548-
nrfx_pwm_irq_handler, &pwm_nrfx_##inst##_data.pwm, 0); \
549-
return pwm_nrfx_init(dev); \
550-
}; \
551-
PM_DEVICE_DT_INST_DEFINE(inst, pwm_nrfx_pm_action); \
552-
DEVICE_DT_INST_DEINIT_DEFINE(inst, \
553-
pwm_nrfx_init##inst, NULL, \
554-
PM_DEVICE_DT_INST_GET(inst), \
555-
&pwm_nrfx_##inst##_data, \
556-
&pwm_nrfx_##inst##_config, \
557-
POST_KERNEL, PWM_INIT_PRIORITY(inst), \
537+
},)) }; \
538+
static int pwm_nrfx_init##inst(const struct device *dev) \
539+
{ \
540+
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), nrfx_pwm_irq_handler, \
541+
&pwm_nrfx_##inst##_data.pwm, 0); \
542+
return pwm_nrfx_init(dev); \
543+
}; \
544+
PM_DEVICE_DT_INST_DEFINE(inst, pwm_nrfx_pm_action); \
545+
DEVICE_DT_INST_DEINIT_DEFINE(inst, pwm_nrfx_init##inst, NULL, PM_DEVICE_DT_INST_GET(inst), \
546+
&pwm_nrfx_##inst##_data, &pwm_nrfx_##inst##_config, \
547+
POST_KERNEL, PWM_INIT_PRIORITY(inst), \
558548
&pwm_nrfx_drv_api_funcs)
559549

560550
DT_INST_FOREACH_STATUS_OKAY(PWM_NRFX_DEFINE)

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