@@ -32,82 +32,4 @@ description: |
3232
3333compatible : " nordic,npm1300-regulator"
3434
35- include : base.yaml
36-
37- properties :
38- dvs-gpios :
39- type : phandle-array
40- description : |
41- List of SOC GPIOs connected to PMIC GPIOs.
42- Set_dvs_mode will drive these pins as follows:
43- DVS mode 1 will enable the first pin
44- DVS mode 2 will enable the second pin
45- DVS mode 3 will drive the first and second pins
46- etc.
47- The effect of the mode change is defined by the enable-gpios
48- and pwm_gpios fields for each of the regulator blocks.
49-
50- child-binding :
51- include :
52- - name : regulator.yaml
53- property-allowlist :
54- - regulator-always-on
55- - regulator-boot-on
56- - regulator-boot-off
57- - regulator-min-microvolt
58- - regulator-max-microvolt
59- - regulator-init-microvolt
60- - regulator-allowed-modes
61- - regulator-initial-mode
62- - regulator-min-microamp
63- - regulator-max-microamp
64- - startup-delay-us
65- - off-on-delay-us
66-
67- properties :
68- retention-microvolt :
69- type : int
70- description : |
71- Retention mode voltage in microvolts.
72-
73- enable-gpio-config :
74- type : array
75- description : |
76- Regulator enable controlled by specified GPIO pin <idx flags>.
77- When set regulator must be enabled/disabled using set_dvs_mode.
78-
79- pwm-gpio-config :
80- type : array
81- description : |
82- Regulator enable controlled by specified GPIO pin <idx flags>.
83- When set regulator must be enabled/disabled using set_dvs_mode.
84-
85- retention-gpio-config :
86- type : array
87- description : |
88- Retention mode controlled by specified GPIO pin <idx flags>.
89-
90- soft-start-microamp :
91- type : int
92- enum :
93- - 10000
94- - 20000
95- - 35000
96- - 50000
97- description : |
98- Soft start current limit in microamps.
99-
100- active-discharge :
101- type : boolean
102- description : |
103- Enable active-discharge on the BUCK/LDO/LDSW output when disabled.
104-
105- nordic,anomaly38-disable-workaround :
106- type : boolean
107- description : |
108- Disable the SW workaround for nPM1300 anomaly #38.
109- When nPM1300 is in ULP mode, LDO is supplied from VSYS and
110- then LDO is enabled, it can take long time until the LDO
111- output has reached its target voltage. To avoid this, an i2c
112- read is performed shortly after an LDO is enabled.
113- See nPM1300 Errata manual for more details.
35+ include : " nordic,npm13xx-regulator-common.yaml"
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