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karstenkoenigkarstenkoenig
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boards: nordic: nrf54h20dk: Add ETM support
Added configuration of coresight peripherals to the cpuapp JLinkScript so the funnels, replicators etc are correctly configured. Signed-off-by: Karsten Koenig <[email protected]>
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‎boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript‎

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__constant U32 _CPUCONF_ADDR = 0x52011000;
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__constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C;
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// ATBFUNNEL
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__constant U32 _ATBFUNNEL211_ADDR = 0xBF04D000;
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__constant U32 _ATBFUNNEL212_ADDR = 0xBF04E000;
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__constant U32 _ATBFUNNEL_CTRLREG_OFFSET = 0x0;
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__constant U32 _HOLDTIME_4 = 0x300;
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__constant U32 _ENS0 = 0x1;
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__constant U32 _ENS1 = 0x2;
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__constant U32 _ENS2 = 0x4;
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// ATBREPLICATOR
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__constant U32 _ATBREPLICATOR212_ADDR = 0xBF04A000;
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__constant U32 _ATBREPLICATOR213_ADDR = 0xBF04B000;
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__constant U32 _ATBREPLICATOR_IDFILTER0_OFFSET = 0x0;
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__constant U32 _ATBREPLICATOR_IDFILTER1_OFFSET = 0x4;
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__constant U32 _ID_NONE = 0xFFFFFFFF;
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__constant U32 _ID1x = 0xFFFFFFFD;
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// TSGEN
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__constant U32 _TSGEN_ADDR = 0xBF041000;
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__constant U32 _TSGEN_CNTCR_OFFSET = 0x0;
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__constant U32 _TSGEN_CNTFID0_OFFSET = 0x20;
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// Clock rate = TDD Freq. / 8
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__constant U32 _TS_CLOCKRATE = 40000000;
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// CTI
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__constant U32 _CTI210_ADDR = 0xBF046000;
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__constant U32 _CTICONTROL_OFFSET = 0x0;
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__constant U32 _CTIOUTEN_OFFSET = 0xA0;
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__constant U32 _CTIGATE_OFFSET = 0x140;
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__constant U32 _TPIU_FLUSH_TRIG = 0x2;
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// GPR
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__constant U32 _GPR_ADDR = 0xbf050000;
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__constant U32 _CPWRUPREQ_OFFSET = 0x0;
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__constant U32 _PWR_TPIU_GPIO_PATH = 0x101;
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// TPIU
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__constant U32 _TPIU_ADDR = 0xBF043000;
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__constant U32 _CURRENTPORTSIZE_OFFSET = 0x4;
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__constant U32 _FFCR_OFFSET = 0x304;
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__constant U32 _FSCR_OFFSET = 0x308;
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__constant U32 _ENFCONT = 0x02;
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__constant U32 _FONFLIN = 0x10;
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__constant U32 _ENFTC = 0x1;
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__constant U32 _TPIU_SYNC_FRAME_COUNT = 0x8;
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__constant U32 _CURRENTPORTSIZE_4 = 0x8;
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// TDDCONF
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__constant U32 _TDDCONF_ADDR = 0xBF001000;
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__constant U32 _TRACEPORTSPEED_OFFSET = 0x408;
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__constant U32 _SPEED80MHZ = 0x0;
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// SPU
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__constant U32 _SPU131_ADDR = 0x5F920000;
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__constant U32 _FEATURE_GPIO_P7_OFFSET = 0xb80;
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__constant U32 _ATTR_SECDOM_SECURE = 0x10010;
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// CoreSight general
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__constant U32 _CORESIGHT_CLAIMSET_OFFSET = 0xFA0;
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__constant U32 _CORESIGHT_CLAIMCLR_OFFSET = 0xFA4;
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__constant U32 _CORESIGHT_LAR_OFFSET = 0xFB0;
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__constant U32 _CORESIGHT_UNLOCK_KEY = 0xC5ACCE55;
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// Settings
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__constant U32 _DEBUGGER_CLAIM_MASK = 0x2;
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// Used to check if we have already set up tracing
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int _needCoresightSetup = 1;
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// Unlock a CoreSight peripheral
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void _CSUnlock(U32 addr)
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{
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JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, _CORESIGHT_UNLOCK_KEY);
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}
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// Lock a CoreSight peripheral
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void _CSLock(U32 addr)
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{
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JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, 0);
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}
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// Set claim bits in the CoreSight peripheral to indicate to the firmware that it
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// has been configured by the host debugger
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void _CSClaim(U32 addr)
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{
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JLINK_MEM_WriteU32(addr + _CORESIGHT_CLAIMSET_OFFSET, _DEBUGGER_CLAIM_MASK);
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}
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// Set up CoreSight and other necessary configuration so to enable ETM -> TPIU tracing.
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int _SetupSecdomTrace(void)
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{
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// Set up ATB funnels/replicators to route ApplicationDomain ETM to TPIU
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_CSUnlock(_ATBFUNNEL212_ADDR);
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JLINK_MEM_WriteU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, _HOLDTIME_4 | _ENS0);
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_CSClaim(_ATBFUNNEL212_ADDR);
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_CSLock(_ATBFUNNEL212_ADDR);
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_CSUnlock(_ATBREPLICATOR212_ADDR);
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JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, _ID_NONE);
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JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, _ID1x);
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_CSLock(_ATBREPLICATOR212_ADDR);
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_CSClaim(_ATBREPLICATOR212_ADDR);
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_CSLock(_ATBREPLICATOR212_ADDR);
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_CSUnlock(_ATBFUNNEL211_ADDR);
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JLINK_MEM_WriteU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, _HOLDTIME_4 | _ENS0);
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_CSClaim(_ATBFUNNEL211_ADDR);
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_CSLock(_ATBFUNNEL211_ADDR);
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_CSUnlock(_ATBREPLICATOR213_ADDR);
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JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, _ID1x);
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JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, _ID_NONE);
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_CSClaim(_ATBREPLICATOR213_ADDR);
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_CSLock(_ATBREPLICATOR213_ADDR);
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// Configure timestamp generator for the correct clock rate
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JLINK_MEM_WriteU32(_TSGEN_ADDR + _TSGEN_CNTFID0_OFFSET, _TS_CLOCKRATE);
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JLINK_MEM_WriteU32(_TSGEN_ADDR + _TSGEN_CNTCR_OFFSET, 1);
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_CSClaim(_TSGEN_ADDR);
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// Configure CTI1 for TPIU formatter flushing
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_CSUnlock(_CTI210_ADDR);
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JLINK_MEM_WriteU32(_CTI210_ADDR + _CTIOUTEN_OFFSET, _TPIU_FLUSH_TRIG);
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JLINK_MEM_WriteU32(_CTI210_ADDR + _CTIGATE_OFFSET, _TPIU_FLUSH_TRIG);
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JLINK_MEM_WriteU32(_CTI210_ADDR + _CTICONTROL_OFFSET, 1);
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_CSClaim(_CTI210_ADDR);
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_CSLock(_CTI210_ADDR);
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// Configure GPR to power on the necessary domains to trace to pins
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_CSUnlock(_GPR_ADDR);
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JLINK_MEM_WriteU32(_GPR_ADDR, _PWR_TPIU_GPIO_PATH);
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_CSClaim(_GPR_ADDR);
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_CSLock(_GPR_ADDR);
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// Configure TPIU for port size 4, continuous formatting
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_CSUnlock(_TPIU_ADDR);
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JLINK_MEM_WriteU32(_TPIU_ADDR + _CURRENTPORTSIZE_OFFSET, _CURRENTPORTSIZE_4);
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JLINK_MEM_WriteU32(_TPIU_ADDR + _FFCR_OFFSET, _ENFCONT | _FONFLIN | _ENFTC);
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JLINK_MEM_WriteU32(_TPIU_ADDR + _FSCR_OFFSET, _TPIU_SYNC_FRAME_COUNT);
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_CSClaim(_TPIU_ADDR);
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_CSLock(_TPIU_ADDR);
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return 0;
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}
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int ConfigTargetSettings(void)
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{
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JLINK_ExecCommand("CORESIGHT_AddAP = Index=0 Type=AHB-AP");
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CORESIGHT_IndexAHBAPToUse = 0;
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// Adjust trace sample delay to compensate for timing when using 320MHz
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JLINK_ExecCommand("TraceSampleAdjust TD = 1000");
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return 0;
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}
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int OnTraceStart(void)
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{
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// Set up CoreSight if not already configured
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if (_needCoresightSetup) {
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_SetupSecdomTrace();
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_needCoresightSetup = 0;
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}
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return 0;
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}
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int SetupTarget(void)
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{
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JLINK_TARGET_Halt();

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