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[Backport v3.7.99-ncs1-branch] [nrf fromtree] boards: nordic: ipc: added dcache alignement #2185

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Oct 29, 2024
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[Backport v3.7.99-ncs1-branch] [nrf fromtree] boards: nordic: ipc: added dcache alignement #2185

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1 change: 1 addition & 0 deletions boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi
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Expand Up @@ -22,6 +22,7 @@

cpuapp_cpurad_ipc: ipc-2-3 {
compatible = "zephyr,ipc-icbmsg";
dcache-alignment = <32>;
status = "disabled";
mboxes = <&cpuapp_bellboard 18>,
<&cpurad_bellboard 12>;
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1 change: 1 addition & 0 deletions boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi
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Expand Up @@ -22,6 +22,7 @@

cpuapp_cpurad_ipc: ipc-2-3 {
compatible = "zephyr,ipc-icbmsg";
dcache-alignment = <32>;
status = "disabled";
mboxes = <&cpuapp_bellboard 18>,
<&cpurad_bellboard 12>;
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10 changes: 10 additions & 0 deletions doc/services/ipc/ipc_service/backends/ipc_service_icbmsg.rst
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Expand Up @@ -40,12 +40,21 @@ Configuration
The backend is configured using Kconfig and devicetree.
When configuring the backend, do the following:

* If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
This must be the largest value of the invalidation or the write-back size for both sides of the communication.
You can skip it if none of the communication sides is using data cache on shared memory.
* Define two memory regions and assign them to ``tx-region`` and ``rx-region`` of an instance.
Ensure that the memory regions used for data exchange are unique (not overlapping any other region) and accessible by both domains (or CPUs).
* Define the number of allocable blocks for each region with ``tx-blocks`` and ``rx-blocks``.
* Define MBOX devices for sending a signal that informs the other domain (or CPU) of the written data.
Ensure that the other domain (or CPU) can receive the signal.

.. caution::

Make sure that you set correct value of the ``dcache-alignment``.
At first, wrong value may not show any signs, which may give a false impression that everything works.
Unstable behavior will appear sooner or later.

See the following configuration example for one of the instances:

.. code-block:: devicetree
Expand All @@ -63,6 +72,7 @@ See the following configuration example for one of the instances:
ipc {
ipc0: ipc0 {
compatible = "zephyr,ipc-icbmsg";
dcache-alignment = <32>;
tx-region = <&tx>;
rx-region = <&rx>;
tx-blocks = <16>;
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10 changes: 10 additions & 0 deletions doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst
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Expand Up @@ -24,6 +24,9 @@ Configuration
The backend is configured via Kconfig and devicetree.
When configuring the backend, do the following:

* If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.
This must be the largest value of the invalidation or the write-back size for both sides of the communication.
You can skip it if none of the communication sides is using data cache on shared memory.
* Define two memory regions and assign them to ``tx-region`` and ``rx-region``
of an instance. Ensure that the memory regions used for data exchange are
unique (not overlapping any other region) and accessible by both domains
Expand All @@ -32,6 +35,12 @@ When configuring the backend, do the following:
domain (or CPU) that data has been written. Ensure that the other domain
(or CPU) is able to receive the signal.

.. caution::

Make sure that you set correct value of the ``dcache-alignment``.
At first, wrong value may not show any signs, which may give a false impression that everything works.
Unstable behavior will appear sooner or later.

See the following configuration example for one of the instances:

.. code-block:: devicetree
Expand All @@ -49,6 +58,7 @@ See the following configuration example for one of the instances:
ipc {
ipc0: ipc0 {
compatible = "zephyr,ipc-icmsg";
dcache-alignment = <32>;
tx-region = <&tx>;
rx-region = <&rx>;
mboxes = <&mbox 0>, <&mbox 1>;
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2 changes: 1 addition & 1 deletion dts/bindings/ipc/zephyr,ipc-icmsg.yaml
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Expand Up @@ -32,7 +32,7 @@ properties:
For example:
Side A: no data cache
Side B: 32 Bytes write-back size, 16 Bytes invalidation size
dcache-alignment = 32; for both
dcache-alignment = <32>; for both

mboxes:
description: phandle to the MBOX controller (TX and RX are required)
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1 change: 1 addition & 0 deletions samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
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Expand Up @@ -23,6 +23,7 @@
ipc {
ipc0: ipc0 {
compatible = "zephyr,ipc-icmsg";
dcache-alignment = <32>;
tx-region = <&sram_tx>;
rx-region = <&sram_rx>;
mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
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1 change: 1 addition & 0 deletions samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp_icbmsg.overlay
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Expand Up @@ -23,6 +23,7 @@
ipc {
ipc0: ipc0 {
compatible = "zephyr,ipc-icbmsg";
dcache-alignment = <32>;
tx-region = <&sram_tx>;
rx-region = <&sram_rx>;
tx-blocks = <16>;
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1 change: 1 addition & 0 deletions samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay
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Expand Up @@ -23,6 +23,7 @@
ipc {
ipc0: ipc0 {
compatible = "zephyr,ipc-icmsg";
dcache-alignment = <32>;
tx-region = <&sram_tx>;
rx-region = <&sram_rx>;
mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
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1 change: 1 addition & 0 deletions ...les/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay
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Expand Up @@ -23,6 +23,7 @@
ipc {
ipc0: ipc0 {
compatible = "zephyr,ipc-icbmsg";
dcache-alignment = <32>;
tx-region = <&sram_tx>;
rx-region = <&sram_rx>;
tx-blocks = <18>;
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4 changes: 2 additions & 2 deletions subsys/ipc/ipc_service/backends/ipc_icbmsg.c
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Expand Up @@ -1434,11 +1434,11 @@
}; \
BUILD_ASSERT(IS_POWER_OF_TWO(GET_CACHE_ALIGNMENT(i)), \
"This module supports only power of two cache alignment"); \
BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, tx, rx) > GET_CACHE_ALIGNMENT(i)) && \
BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, tx, rx) >= GET_CACHE_ALIGNMENT(i)) && \
(GET_BLOCK_SIZE_INST(i, tx, rx) < \
GET_MEM_SIZE_INST(i, tx)), \
"TX region is too small for provided number of blocks"); \
BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, rx, tx) > GET_CACHE_ALIGNMENT(i)) && \
BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, rx, tx) >= GET_CACHE_ALIGNMENT(i)) && \
(GET_BLOCK_SIZE_INST(i, rx, tx) < \
GET_MEM_SIZE_INST(i, rx)), \
"RX region is too small for provided number of blocks"); \
Expand All @@ -1452,5 +1452,5 @@
POST_KERNEL, \
CONFIG_IPC_SERVICE_REG_BACKEND_PRIORITY, \
&backend_ops);

Check notice on line 1455 in subsys/ipc/ipc_service/backends/ipc_icbmsg.c

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subsys/ipc/ipc_service/backends/ipc_icbmsg.c:1455 
-#define DEFINE_BACKEND_DEVICE(i)							\
-	SYS_BITARRAY_DEFINE_STATIC(tx_usage_bitmap_##i, DT_INST_PROP(i, tx_blocks));	\
-	SYS_BITARRAY_DEFINE_STATIC(rx_hold_bitmap_##i, DT_INST_PROP(i, rx_blocks));	\
-	PBUF_DEFINE(tx_icbmsg_pb_##i,							\
-			GET_MEM_ADDR_INST(i, tx),					\
-			GET_ICMSG_SIZE_INST(i, tx, rx),					\
-			GET_CACHE_ALIGNMENT(i));					\
-	PBUF_DEFINE(rx_icbmsg_pb_##i,							\
-			GET_MEM_ADDR_INST(i, rx),					\
-			GET_ICMSG_SIZE_INST(i, rx, tx),					\
-			GET_CACHE_ALIGNMENT(i));					\
-	static struct backend_data backend_data_##i = {					\
-		.control_data = {							\
-			.tx_pb = &tx_icbmsg_pb_##i,					\
-			.rx_pb = &rx_icbmsg_pb_##i,					\
-		}									\
-	};										\
-	static MAYBE_CONST struct icbmsg_config backend_config_##i =			\
-	{										\
-		.control_config = {							\
-			.mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx),			\
-			.mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx),			\
-		},									\
-		.tx = {									\
-			.blocks_ptr = (uint8_t *)GET_BLOCKS_ADDR_INST(i, tx, rx),	\
-			.block_count = DT_INST_PROP(i, tx_blocks),			\
-			.block_size = GET_BLOCK_SIZE_INST(i, tx, rx),			\
-		},									\
-		.rx = {									\
-			.blocks_ptr = (uint8_t *)GET_BLOCKS_ADDR_INST(i, rx, tx),	\
-			.block_count = DT_INST_PROP(i, rx_blocks),			\
-			.block_size = GET_BLOCK_SIZE_INST(i, rx, tx),			\
-		},									\
-		.tx_usage_bitmap = &tx_usage_bitmap_##i,				\
-		.rx_hold_bitmap = &rx_hold_bitmap_##i,					\
-	};										\
-	BUILD_ASSERT(IS_POWER_OF_TWO(GET_CACHE_ALIGNMENT(i)),				\
-		     "This module supports only power of two cache alignment");		\
-	BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, tx, rx) >= GET_CACHE_ALIGNMENT(i)) &&	\
-		     (GET_BLOCK_SIZE_INST(i, tx, rx) <					\
-		      GET_MEM_SIZE_INST(i, tx)),					\
-		     "TX region is too small for provided number of blocks");		\
-	BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, rx, tx) >= GET_CACHE_ALIGNMENT(i)) &&	\
-		     (GET_BLOCK_SIZE_INST(i, rx, tx) <					\
-		      GET_MEM_SIZE_INST(i, rx)),					\
-		     "RX region is too small for provided number of blocks");		\
-	BUILD_ASSERT(DT_INST_PROP(i, rx_blocks) <= 256, "Too many RX blocks");		\
-	BUILD_ASSERT(DT_INST_PROP(i, tx_blocks) <= 256, "Too many TX blocks");		\
-	DEVICE_DT_INST_DEFINE(i,							\
-			      &backend_init,						\
-			      NULL,							\
-			      &backend_data_##i,					\
-			      &backend_config_##i,					\
-			      POST_KERNEL,						\
-			      CONFIG_IPC_SERVICE_REG_BACKEND_PRIORITY,			\
-			      &backend_ops);
+#define DEFINE_BACKEND_DEVICE(i)                                                                   \
+	SYS_BITARRAY_DEFINE_STATIC(tx_usage_bitmap_##i, DT_INST_PROP(i, tx_blocks));               \
+	SYS_BITARRAY_DEFINE_STATIC(rx_hold_bitmap_##i, DT_INST_PROP(i, rx_blocks));                \
+	PBUF_DEFINE(tx_icbmsg_pb_##i, GET_MEM_ADDR_INST(i, tx), GET_ICMSG_SIZE_INST(i, tx, rx),    \
+		    GET_CACHE_ALIGNMENT(i));                                                       \
+	PBUF_DEFINE(rx_icbmsg_pb_##i, GET_MEM_ADDR_INST(i, rx), GET_ICMSG_SIZE_INST(i, rx, tx),    \
+		    GET_CACHE_ALIGNMENT(i));                                                       \
+	static struct backend_data backend_data_##i = {.control_data = {                           \
+							       .tx_pb = &tx_icbmsg_pb_##i,         \
+							       .rx_pb = &rx_icbmsg_pb_##i,         \
+						       }};                                         \
+	static MAYBE_CONST struct icbmsg_config backend_config_##i = {                             \
+		.control_config =                                                                  \
+			{                                                                          \
+				.mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx),                           \
+				.mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx),                           \
+			},                                                                         \
+		.tx =                                                                              \
+			{
DT_INST_FOREACH_STATUS_OKAY(DEFINE_BACKEND_DEVICE)
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