Skip to content

[nrf fromlist] soc: nordic: dmm: Fix DMM_REG_ALIGN_SIZE macro when CO… #2210

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Nov 1, 2024
Merged

[nrf fromlist] soc: nordic: dmm: Fix DMM_REG_ALIGN_SIZE macro when CO… #2210

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
18 changes: 13 additions & 5 deletions soc/nordic/common/dmm.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -23,19 +23,27 @@

/** @cond INTERNAL_HIDDEN */

#ifdef CONFIG_DCACHE

/* Determine if memory region is cacheable. */
#define DMM_IS_REG_CACHEABLE(node_id) \
COND_CODE_1(CONFIG_DCACHE, \
(COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), \
((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \
(0))), (0))
#define DMM_IS_REG_CACHEABLE(node_id) \
COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), \
((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \
(0))

Check notice on line 33 in soc/nordic/common/dmm.h

View workflow job for this annotation

GitHub Actions / Run compliance checks on patch series (PR)

You may want to run clang-format on this change 

soc/nordic/common/dmm.h:33 
-#define DMM_IS_REG_CACHEABLE(node_id)					     \
-	COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr),	     \
-		((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \
-		(0))
+#define DMM_IS_REG_CACHEABLE(node_id)                                                              \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr),                                 \
+		    ((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), (0))
/* Determine required alignment of the data buffers in specified memory region.
* Cache line alignment is required if region is cacheable and data cache is enabled.
*/
#define DMM_REG_ALIGN_SIZE(node_id) \
(DMM_IS_REG_CACHEABLE(node_id) ? CONFIG_DCACHE_LINE_SIZE : sizeof(uint8_t))

#else

#define DMM_IS_REG_CACHEABLE(node_id) 0
#define DMM_REG_ALIGN_SIZE(node_id) (sizeof(uint8_t))

Check notice on line 44 in soc/nordic/common/dmm.h

View workflow job for this annotation

GitHub Actions / Run compliance checks on patch series (PR)

You may want to run clang-format on this change 

soc/nordic/common/dmm.h:44 
-#define DMM_REG_ALIGN_SIZE(node_id) (sizeof(uint8_t))
+#define DMM_REG_ALIGN_SIZE(node_id)   (sizeof(uint8_t))
#endif /* CONFIG_DCACHE */

/* Determine required alignment of the data buffers in memory region
* associated with specified device node.
*/
Expand Down
Loading