Nrfx 5244 align i2 s tests to tdm

.github/workflows/commit-tags.yml

@@ -0,0 +1,28 @@
+name: Commit tags
+
+on:
+  pull_request:
+    types: [synchronize, opened, reopened, edited, labeled, unlabeled,
+            milestoned, demilestoned, assigned, unassigned, ready_for_review,
+            review_requested]
+
+jobs:
+  commit_tags:
+    runs-on: ubuntu-22.04
+    name: Run commit tags checks on patch series (PR)
+    steps:
+    - name: Update PATH for west
+      run: |
+        echo "$HOME/.local/bin" >> $GITHUB_PATH
+
+    - name: Checkout the code
+      uses: actions/checkout@v3
+      with:
+        ref: ${{ github.event.pull_request.head.sha }}
+        fetch-depth: 0
+
+    - name: Run the commit tags
+      uses: nrfconnect/action-commit-tags@main
+      with:
+        target: .
+        upstream: zephyrproject-rtos/zephyr/main

.github/workflows/compliance.yml

@@ -49,8 +49,8 @@ jobs:
         git config --global user.name "Your Name"
         git remote -v
         # Ensure there's no merge commits in the PR
-        [[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \
-        (echo "::error ::Merge commits not allowed, rebase instead";false)
+        #[[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \
+        #(echo "::error ::Merge commits not allowed, rebase instead";false)
         git rebase origin/${BASE_REF}
         # debug
         git log  --pretty=oneline | head -n 10
@@ -78,8 +78,8 @@ jobs:
         git log  --pretty=oneline | head -n 10
         # Increase rename limit to allow for large PRs
         git config diff.renameLimit 10000
-        ./scripts/ci/check_compliance.py --annotate -e KconfigBasic \
-        -c origin/${BASE_REF}..
+        ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -e Kconfig \
+        -e KconfigBasicNoModules -e ModulesMaintainers -c origin/${BASE_REF}..
 
     - name: upload-results
       uses: actions/upload-artifact@v4

.github/workflows/manifest-PR.yml

@@ -0,0 +1,17 @@
+name: handle manifest PR
+on:
+  pull_request_target:
+    types: [opened, synchronize, closed]
+    branches:
+      - main
+
+
+jobs:
+  call-manifest-pr-action:
+    runs-on: ubuntu-latest
+    steps:
+      - name: handle manifest PR
+        uses: nrfconnect/action-manifest-pr@main
+        with:
+          token: ${{ secrets.NCS_GITHUB_TOKEN }}
+          manifest-pr-title-details: ${{ github.event.pull_request.title }}

CMakeLists.txt

@@ -2232,3 +2232,10 @@ add_subdirectory_ifdef(
   CONFIG_MAKEFILE_EXPORTS
   cmake/makefile_exports
   )
+
+yaml_context(EXISTS NAME build_info result)
+if(result)
+  build_info(zephyr version VALUE ${PROJECT_VERSION_STR})
+  build_info(zephyr zephyr-base VALUE ${ZEPHYR_BASE})
+  yaml_save(NAME build_info)
+endif()

CODEOWNERS

@@ -18,6 +18,7 @@
 # component or code. This file is going to be deprecated and currently only had
 # entries that are not covered by the MAINTAINERS file.
 
+/.github/test-spec.yml                    @nrfconnect/ncs-test-leads
 /soc/arm/aspeed/                          @aspeeddylan
 /soc/atmel/                               @nandojve
 /soc/arm/bcm*/                            @sbranden

Jenkinsfile

@@ -0,0 +1,5 @@
+@Library("CI_LIB") _
+
+def pipeline = new ncs.sdk_zephyr.Main()
+
+pipeline.run(JOB_NAME)

Kconfig.zephyr

@@ -17,13 +17,13 @@ osource "${APPLICATION_SOURCE_DIR}/VERSION"
 # Shield defaults should have precedence over board defaults, which should have
 # precedence over SoC defaults, so include them in that order.
 #
-# $ARCH and $BOARD_DIR will be glob patterns when building documentation.
+# $ARCH and $KCONFIG_BOARD_DIR will be glob patterns when building documentation.
 # This loads custom shields defconfigs (from BOARD_ROOT)
 osource "$(KCONFIG_BINARY_DIR)/Kconfig.shield.defconfig"
 # This loads Zephyr base shield defconfigs
 source "boards/shields/*/Kconfig.defconfig"
 
-osource "$(BOARD_DIR)/Kconfig.defconfig"
+osource "$(KCONFIG_BOARD_DIR)/Kconfig.defconfig"
 
 # This loads Zephyr specific SoC root defconfigs
 source "$(KCONFIG_BINARY_DIR)/soc/Kconfig.defconfig"
@@ -536,11 +536,10 @@ config NO_OPTIMIZATIONS
 endchoice
 
 config LTO
-	bool "Link Time Optimization [EXPERIMENTAL]"
+	bool "Link Time Optimization"
 	depends on !(GEN_ISR_TABLES || GEN_IRQ_VECTOR_TABLE) || ISR_TABLES_LOCAL_DECLARATION
 	depends on !NATIVE_LIBRARY
 	depends on !CODE_DATA_RELOCATION
-	select EXPERIMENTAL
 	help
 	  This option enables Link Time Optimization.
 

MAINTAINERS.yml

@@ -975,7 +975,6 @@ Documentation:
     - doc/images/Zephyr-Kite-in-tree.png
     - doc/index-tex.rst
     - doc/index.rst
-    - doc/kconfig.rst
     - doc/templates/sample.tmpl
     - doc/templates/board.tmpl
     - boards/index.rst
@@ -1157,6 +1156,23 @@ Release Notes:
   tests:
     - drivers.clock
 
+"Drivers: Comparator":
+  status: maintained
+  maintainers:
+    - bjarki-andreasen
+  files:
+    - drivers/comparator/
+    - dts/bindings/comparator/
+    - include/zephyr/drivers/comparator.h
+    - include/zephyr/drivers/comparator/
+    - tests/drivers/build_all/comparator/
+    - tests/drivers/comparator/
+    - doc/hardware/peripherals/comparator.rst
+  labels:
+    - "area: Comparator"
+  tests:
+    - drivers.comparator
+
 "Drivers: Console":
   status: odd fixes
   files:

arch/arm/core/cortex_a_r/Kconfig

@@ -93,6 +93,14 @@ config CPU_CORTEX_R7
 	help
 	  This option signifies the use of a Cortex-R7 CPU
 
+config CPU_CORTEX_R8
+	bool
+	select CPU_AARCH32_CORTEX_R
+	select ARMV7_R
+	select ARMV7_R_FP if CPU_HAS_FPU
+	help
+	  This option signifies the use of a Cortex-R8 CPU
+
 config CPU_CORTEX_R52
 	bool
 	select CPU_AARCH32_CORTEX_R

arch/arm/core/cortex_m/fault.c

@@ -743,7 +743,7 @@ static inline bool z_arm_is_pc_valid(uintptr_t pc)
 		return true;
 	}
 
-#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_itcm))
 	/* Is it in the ITCM */
 	if ((((uintptr_t)&__itcm_start) <= pc) && (pc < ((uintptr_t)&__itcm_end))) {
 		return true;

arch/arm/core/cortex_m/pm_s2ram.S

@@ -70,7 +70,9 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
 	/*
 	 * Mark entering suspend to RAM.
 	 */
-	bl pm_s2ram_mark_set
+	mov 	r1, lr
+	bl 	pm_s2ram_mark_set
+	mov	lr, r1
 
 	/*
 	 * Call the system_off function passed as parameter. This should never
@@ -83,12 +85,19 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
 	 * not successful (in r0 the return value).
 	 */
 
+	/* Move return value of system_off to callee-saved register. */
+	mov 	r4, r0
+
 	/*
 	 * Reset the marking of suspend to RAM, return is ignored.
 	 */
-	bl pm_s2ram_mark_check_and_clear
+	mov 	r1, lr
+	bl	pm_s2ram_mark_check_and_clear
+	mov 	lr, r1
 
-	/* Move system_off back to r0 as return value */
+	/* Move the stored return value of system_off back to r0,
+	 * setting it as return value for this function.
+	 */
 	mov	r0, r4
 
 	pop	{r4-r12, lr}
@@ -99,16 +108,13 @@ GTEXT(arch_pm_s2ram_resume)
 SECTION_FUNC(TEXT, arch_pm_s2ram_resume)
 	/*
 	 * Check if reset occurred after suspending to RAM.
-	 * Store LR to ensure we can continue boot when we are not suspended
-	 * to RAM. In addition to LR, R0 is pushed too, to ensure "SP mod 8 = 0",
-	 * as stated by ARM rule 6.2.1.2 for AAPCS32.
 	 */
-	push    {r0, lr}
-	bl      pm_s2ram_mark_check_and_clear
-	cmp	r0, #0x1
-	pop     {r0, lr}
-	beq	resume
-	bx	lr
+	mov 	r1, lr
+	bl 	pm_s2ram_mark_check_and_clear
+	mov 	lr, r1
+	cmp     r0, #0x1
+	beq     resume
+	bx      lr
 
 resume:
 	/*

arch/arm/core/cortex_m/pm_s2ram.c

@@ -22,20 +22,44 @@ __noinit _cpu_context_t _cpu_context;
  */
 static __noinit uint32_t marker;
 
-void pm_s2ram_mark_set(void)
+void __attribute__((naked)) pm_s2ram_mark_set(void)
 {
-	marker = MAGIC;
+	__asm__ volatile(
+		/* Set the marker to MAGIC value */
+		"str	%[_magic_val], [%[_marker]]\n"
+
+		"bx	lr\n"
+		:
+		: [_magic_val] "r"(MAGIC), [_marker] "r"(&marker)
+		: "r1", "r4", "memory");
 }
 
-bool pm_s2ram_mark_check_and_clear(void)
+bool __attribute__((naked)) pm_s2ram_mark_check_and_clear(void)
 {
-	if (marker == MAGIC) {
-		marker = 0;
+	__asm__ volatile(
+		/* Set return value to 0 */
+		"mov	r0, #0\n"
+
+		/* Check the marker */
+		"ldr	r3, [%[_marker]]\n"
+		"cmp	r3, %[_magic_val]\n"
+		"bne	exit\n"
+
+		/*
+		 * Reset the marker
+		 */
+		"str	r0, [%[_marker]]\n"
 
-		return true;
-	}
+		/*
+		 * Set return value to 1
+		 */
+		"mov	r0, #1\n"
 
-	return false;
+		"exit:\n"
+		"bx lr\n"
+		:
+		: [_magic_val] "r"(MAGIC), [_marker] "r"(&marker)
+		: "r0", "r1", "r3", "r4", "memory");
 }
 
 #endif /* CONFIG_PM_S2RAM_CUSTOM_MARKING */

arch/arm/core/mpu/arm_mpu_regions.c

@@ -8,6 +8,9 @@
 #include <zephyr/arch/arm/mpu/arm_mpu.h>
 
 #include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
+#if USE_PARTITION_MANAGER
+#include <pm_config.h>
+#endif
 
 static const struct arm_mpu_region mpu_regions[] = {
 	/* Region 0 */
@@ -21,13 +24,23 @@ static const struct arm_mpu_region mpu_regions[] = {
 #endif
 	/* Region 1 */
 	MPU_REGION_ENTRY("SRAM_0",
+#if USE_PARTITION_MANAGER
+			 PM_SRAM_ADDRESS,
+#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
+			 REGION_RAM_ATTR(PM_SRAM_ADDRESS, PM_SRAM_SIZE)),
+#else
+			 REGION_RAM_ATTR(REGION_SRAM_SIZE)),
+#endif
+#else
 			 CONFIG_SRAM_BASE_ADDRESS,
 #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
 			 REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \
 				 CONFIG_SRAM_SIZE * 1024)),
 #else
 			 REGION_RAM_ATTR(REGION_SRAM_SIZE)),
 #endif
+
+#endif /* USE_PARTITION_MANAGER */
 };
 
 const struct arm_mpu_config mpu_config = {

boards/01space/esp32c3_042_oled/board.yml

@@ -1,5 +1,6 @@
 board:
   name: esp32c3_042_oled
+  full_name: ESP32C3 0.42 OLED
   vendor: 01space
   socs:
   - name: esp32c3

boards/96boards/aerocore2/board.yml

@@ -1,5 +1,6 @@
 board:
   name: 96b_aerocore2
+  full_name: Aerocore2
   vendor: 96boards
   socs:
     - name: stm32f427xx

boards/96boards/argonkey/board.yml

@@ -1,5 +1,6 @@
 board:
   name: 96b_argonkey
+  full_name: Argonkey
   vendor: 96boards
   socs:
     - name: stm32f412cx

boards/96boards/avenger96/board.yml

@@ -1,5 +1,6 @@
 board:
   name: 96b_avenger96
+  full_name: Avenger96
   vendor: 96boards
   socs:
     - name: stm32mp157cxx

boards/96boards/carbon/board.yml

@@ -1,5 +1,6 @@
 board:
   name: 96b_carbon
+  full_name: Carbon
   vendor: 96boards
   socs:
   - name: stm32f401xe

boards/96boards/meerkat96/board.yml

@@ -1,5 +1,6 @@
 board:
   name: 96b_meerkat96
+  full_name: Meerkat96
   vendor: 96boards
   socs:
     - name: mcimx7d

boards/96boards/neonkey/board.yml

@@ -1,5 +1,6 @@
 board:
   name: 96b_neonkey
+  full_name: Neonkey
   vendor: 96boards
   socs:
     - name: stm32f411xe

boards/96boards/nitrogen/board.yml

@@ -1,5 +1,6 @@
 board:
   name: 96b_nitrogen
+  full_name: Nitrogen
   vendor: 96boards
   socs:
   - name: nrf52832

boards/96boards/stm32_sensor_mez/board.yml

@@ -1,5 +1,6 @@
 board:
   name: 96b_stm32_sensor_mez
+  full_name: STM32 Sensor Mezzanine
   vendor: st
   socs:
     - name: stm32f446xx

boards/96boards/wistrio/board.yml

@@ -1,5 +1,6 @@
 board:
   name: 96b_wistrio
+  full_name: WisTrio
   vendor: 96boards
   socs:
     - name: stm32l151xba