Cherry-pick USB fixes for NCS 2.9.0 #2321
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Low Power mode can only be entered when there are no active DMA transfers. Move the Suspend and Resume processing to thread to allow waiting for the DMA available semaphore in USB Suspend handler. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit 4dfae0b)
DMA transfers do not execute when the USBD peripheral is in Low Power mode. Make sure that there is no DMA active transfer when entering Low Power mode and that new DMA transfers are not started when in Low Power mode because the transfer won't ever finish. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit cb1e7d6)
…Interface Respond with a Request Error in default and addressed states. Signed-off-by: Johann Fischer <[email protected]> (cherry picked from commit 1a5ab2c) Signed-off-by: Tomasz Moń <[email protected]>
The NAKSts bit may be set on isochronous OUT endpoints when incomplete ISO OUT interrupt is raised. The code would then assume that endpoint is already disabled and would not perform the endpoint disable procedure. This in turn was essentially halting any transmission on the isochronous endpoint, abruptly terminating the data stream. Fix the issue by always following full endpoint disable procedure on isochronous endpoints. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit 8b212d8)
… IN interrupt When handling incomplete iso IN interrupt mark current transfer as complete and program the endpoint with any subsequently queued packet. Program the endpoint directly in interrupt handler because the data must be programmed before SOF (by the time incomplete iso IN interrupt is raised there is less than 20% * 125 us = 25 us before SOF). Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit edbb053)
…dpoints Application is expected to call usbd_uac2_send() on each enabled USB Streaming Output Terminal (isochronous IN data endpoint) exactly once every SOF. The class is bookkeeping queued transfers to make it easier to determine component at fault when things go wrong. However, this approach only works fine if the underlying USB device controller buffers the data to be sent on next SOF and reports the transfer completion immediately after data is buffered (e.g. nRF52 USBD). While DWC2 otg also requires the SW to arm endpoint with data for the next SOF, unlike nRF52 USBD the transfer is only considered complete after either the IN token for isochronous endpoint is received or after the Periodic Frame Interval elapses without IN token. This design inevitably requires the application to be able to have at least two buffers for isochronous IN endpoints. Support dual buffering on IN data endpoints to facilitate sending isochronous IN data on every SOF regardless of the underlying USB device controller design. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit c19d34c)
…ndition Endpoint disable function is racing against bus traffic. If the bus traffic leads to transfer completion immediately before the endpoint disable is executed, then the transfer complete interrupt will remain set when the endpoint is disabled. For OUT endpoints this leads to "No buffer for ep" errors, while for IN endpoint this can lead to double buffer pull which causes assertion failure. The proper solution would be to change endpoint disable to not actually wait for the individual events (and accept that the endpoint may not need to be disabled because the transfer can just finish). For the time being workaround the issue by clearing XferCompl bit on endpoint disable. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit a26d3c2)
Accessing DWC2 otg core registers before the clock starts results in complete system hang. Add a 1 us busy wait to make sure that software won't access registers before the clock is started. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit df36b16)
tmon-nordic
requested review from
MarekPieta,
carlescufi,
jfischer-no and
rick1082
bjarki-andreasen
approved these changes
Dec 2, 2024
carlescufi
approved these changes
Dec 2, 2024
jfischer-no
approved these changes
Dec 2, 2024
gmarull
approved these changes
Dec 2, 2024
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
5 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Prevent nRF52/nRF53 USBD DMA transfer in Low Power mode (because it won't work).
Fixes for UAC2 High-Speed support on nRF54H20.