[nrf fromlist] drivers: pwm: nrfx: add global hsfll request for fast PWM

drivers/clock_control/clock_control_nrf2_common.c

@@ -4,6 +4,7 @@
  */
 
 #include "clock_control_nrf2_common.h"
+#include <zephyr/drivers/clock_control/nrf_clock_control.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(clock_control_nrf2, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
@@ -24,6 +25,13 @@
  */
 STRUCT_CLOCK_CONFIG(generic, ONOFF_CNT_MAX);
 
+/* Structure used for synchronous clock request. */
+struct sync_req {
+	struct onoff_client cli;
+	struct k_sem sem;
+	int res;
+};
+
 static void update_config(struct clock_config_generic *cfg)
 {
 	atomic_val_t prev_flags = atomic_or(&cfg->flags, FLAG_UPDATE_NEEDED);
@@ -159,3 +167,39 @@
 
 	return -ENOSYS;
 }
+
+static void sync_cb(struct onoff_manager *mgr, struct onoff_client *cli, uint32_t state, int res)
+{
+	struct sync_req *req = CONTAINER_OF(cli, struct sync_req, cli);
+
+	req->res = res;
+	k_sem_give(&req->sem);
+}
+
+int nrf_clock_control_request_sync(const struct device *dev,
+				   const struct nrf_clock_spec *spec,
+				   k_timeout_t timeout)
+{
+	struct sync_req req = {
+		.sem = Z_SEM_INITIALIZER(req.sem, 0, 1)
+	};
+	int err;
+
+	if (k_is_in_isr()) {
+		return -EWOULDBLOCK;
+	}
+
+	sys_notify_init_callback(&req.cli.notify, sync_cb);
+
+	err = nrf_clock_control_request(dev, spec, &req.cli);
+	if (err < 0) {
+		return err;
+	}
+
+	err = k_sem_take(&req.sem, timeout);
+	if (err < 0) {
+		return err;
+	}
+
+	return req.res;
+}

drivers/pwm/pwm_nrfx.c

@@ -13,6 +13,9 @@
 #include <zephyr/linker/devicetree_regions.h>
 #include <zephyr/cache.h>
 #include <zephyr/mem_mgmt/mem_attr.h>
+#ifdef CONFIG_CLOCK_CONTROL
+#include <zephyr/drivers/clock_control/nrf_clock_control.h>
+#endif
 #ifdef CONFIG_SOC_NRF54H20_GPD
 #include <nrf/gpd.h>
 #endif
@@ -35,6 +38,26 @@
 #define ANOMALY_109_EGU_IRQ_CONNECT(idx)
 #endif
 
+#define PWM(dev_idx) DT_NODELABEL(pwm##dev_idx)
+#define PWM_PROP(dev_idx, prop) DT_PROP(PWM(dev_idx), prop)
+#define PWM_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(PWM(idx), prop)
+
+#define PWM_NRFX_IS_FAST(unused, prefix, idx, _)					\
+	COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(PWM(idx)),					\
+		(COND_CODE_1(PWM_HAS_PROP(idx, power_domains),				\
+		    (IS_EQ(DT_PHA(PWM(idx), power_domains, id), NRF_GPD_FAST_ACTIVE1)),	\
+		    (0))), (0))
+
+#if NRFX_FOREACH_PRESENT(PWM, PWM_NRFX_IS_FAST, (||), (0))
+#if CONFIG_CLOCK_CONTROL
+#define PWM_NRFX_USE_CLOCK_CONTROL 1
+#endif
+#define PWM_NRFX_INIT_PRIORITY 99
+#else
+#define PWM_NRFX_INIT_PRIORITY CONFIG_PWM_INIT_PRIORITY
+#endif
+
+
 #define PWM_NRFX_CH_POLARITY_MASK BIT(15)
 #define PWM_NRFX_CH_COMPARE_MASK  BIT_MASK(15)
 #define PWM_NRFX_CH_VALUE(compare_value, inverted) \
@@ -49,6 +72,10 @@
 #ifdef CONFIG_DCACHE
 	uint32_t mem_attr;
 #endif
+#ifdef PWM_NRFX_USE_CLOCK_CONTROL
+	const struct device *clk_dev;
+	struct nrf_clock_spec clk_spec;
+#endif
 };
 
 struct pwm_nrfx_data {
@@ -57,6 +84,9 @@
 	uint8_t  pwm_needed;
 	uint8_t  prescaler;
 	bool     stop_requested;
+#ifdef PWM_NRFX_USE_CLOCK_CONTROL
+	bool     clock_requested;
+#endif
 };
 /* Ensure the pwm_needed bit mask can accommodate all available channels. */
 #if (NRF_PWM_CHANNEL_COUNT > 8)
@@ -229,6 +259,18 @@
 		 * ensure it is stopped before starting the next playback.
 		 */
 		nrfx_pwm_stop(&config->pwm, false);
+#if PWM_NRFX_USE_CLOCK_CONTROL
+		if (data->clock_requested) {
+			int ret = nrf_clock_control_release(config->clk_dev, &config->clk_spec);
+
+			if (ret < 0) {
+				LOG_ERR("Global HSFLL release failed: %d", ret);
+				return ret;
+			}
+
+			data->clock_requested = false;
+		}
+#endif
 		data->stop_requested = true;
 	} else {
 		if (data->stop_requested) {
@@ -248,6 +290,18 @@
 		 * until another playback is requested (new values will be
 		 * loaded then) or the PWM peripheral is stopped.
 		 */
+#if PWM_NRFX_USE_CLOCK_CONTROL
+
+		int ret = nrf_clock_control_request_sync(config->clk_dev, &config->clk_spec,
+							 K_FOREVER);
+
+		if (ret < 0) {
+			LOG_ERR("Global HSFLL request failed: %d", ret);
+			return ret;
+		}
+
+		data->clock_requested = true;
+#endif
 		nrfx_pwm_simple_playback(&config->pwm, &config->seq, 1,
 					 NRFX_PWM_FLAG_NO_EVT_FINISHED);
 	}
@@ -306,6 +360,14 @@
 	const struct pwm_nrfx_config *config = dev->config;
 
 	nrfx_pwm_stop(&config->pwm, false);
+#if PWM_NRFX_USE_CLOCK_CONTROL
+
+		int ret = nrf_clock_control_release(config->clk_dev, &config->clk_spec);
+
+		if (ret < 0) {
+			LOG_ERR("Global HSFLL release failed: %d", ret);
+		}
+#endif
 	while (!nrfx_pwm_stopped_check(&config->pwm)) {
 	}
 
@@ -351,9 +413,6 @@
 	return pm_device_driver_init(dev, pwm_nrfx_pm_action);
 }
 
-#define PWM(dev_idx) DT_NODELABEL(pwm##dev_idx)
-#define PWM_PROP(dev_idx, prop) DT_PROP(PWM(dev_idx), prop)
-#define PWM_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(PWM(idx), prop)
 #define PWM_MEM_REGION(idx)     DT_PHANDLE(PWM(idx), memory_regions)
 
 #define PWM_MEMORY_SECTION(idx)						      \
@@ -393,6 +452,15 @@
 			(16ul * 1000ul * 1000ul)),			      \
 		IF_ENABLED(CONFIG_DCACHE,				      \
 			(.mem_attr = PWM_GET_MEM_ATTR(idx),))		      \
+		IF_ENABLED(PWM_NRFX_USE_CLOCK_CONTROL,		      \
+			(.clk_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(PWM(idx))),  \
+			 .clk_spec = {					      \
+				.frequency =				      \
+					NRF_PERIPH_GET_FREQUENCY(PWM(idx)),   \
+				.accuracy = 0,				      \
+				.precision =				      \
+					NRF_CLOCK_CONTROL_PRECISION_DEFAULT,  \
+			 },))						      \
 	};								      \
 	static int pwm_nrfx_init##idx(const struct device *dev)		      \
 	{								      \
@@ -405,9 +473,9 @@
 			 pwm_nrfx_init##idx, PM_DEVICE_DT_GET(PWM(idx)),      \
 			 &pwm_nrfx_##idx##_data,			      \
 			 &pwm_nrfx_##idx##_config,			      \
-			 POST_KERNEL, CONFIG_PWM_INIT_PRIORITY,		      \
+			 POST_KERNEL, PWM_NRFX_INIT_PRIORITY,		      \
 			 &pwm_nrfx_drv_api_funcs)
 
 #define COND_PWM_NRFX_DEVICE(unused, prefix, i, _) \
 	IF_ENABLED(CONFIG_HAS_HW_NRF_PWM##prefix##i, (PWM_NRFX_DEVICE(prefix##i);))
 

include/zephyr/devicetree.h

@@ -809,6 +809,17 @@
 #define DT_PROP_BY_IDX(node_id, prop, idx) \
 	DT_CAT5(node_id, _P_, prop, _IDX_, idx)
 
+/**
+ * @brief Get the last element of an array type property
+ *
+ * @param node_id node identifier
+ * @param prop lowercase-and-underscores property name
+ *
+ * @return a representation of the last element of the property
+ */
+#define DT_PROP_LAST(node_id, prop) \
+	DT_PROP_BY_IDX(node_id, prop, UTIL_DEC(DT_PROP_LEN(node_id, prop)))
+
 /**
  * @brief Like DT_PROP(), but with a fallback to @p default_value
  *

include/zephyr/drivers/clock_control/nrf_clock_control.h

@@ -235,6 +235,23 @@
 	return api->request(dev, spec, cli);
 }
 
+/**
+ * @brief Synchronously request a reservation to use a given clock with specified attributes.
+ *
+ * @see nrf_clock_control_request().
+ *
+ * @param dev pointer to the clock device structure.
+ * @param spec See nrf_clock_control_request().
+ * @param timeout Request timeout.
+ *
+ * @retval 0 if request is fulfilled.
+ * @retval -EWOULDBLOCK if request is called from the interrupt context.
+ * @retval negative See error codes returned by nrf_clock_control_request().
+ */
+int nrf_clock_control_request_sync(const struct device *dev,
+				   const struct nrf_clock_spec *spec,
+				   k_timeout_t timeout);
+
 /**
  * @brief Release a reserved use of a clock.
  *
@@ -294,6 +311,25 @@
 
 #endif /* defined(CONFIG_CLOCK_CONTROL_NRF2) */
 
+/** @brief Get clock frequency that is used for the given node.
+ *
+ * Macro checks if node has clock property and if yes then if clock has clock_frequency property
+ * then it is returned. If it has supported_clock_frequency property with the list of supported
+ * frequencies then the last one is returned with assumption that they are ordered and the last
+ * one is the highest. If node does not have clock then 16 MHz is returned which is the default
+ * frequency.
+ *
+ * @param node Devicetree node.
+ *
+ * @return Frequency of the clock that is used for the node.
+ */
+#define NRF_PERIPH_GET_FREQUENCY(node) \
+	COND_CODE_1(DT_CLOCKS_HAS_IDX(node, 0),							\
+		(COND_CODE_1(DT_NODE_HAS_PROP(DT_CLOCKS_CTLR(node), clock_frequency),		\
+			     (DT_PROP(DT_CLOCKS_CTLR(node), clock_frequency)),			\
+			     (DT_PROP_LAST(DT_CLOCKS_CTLR(node), supported_clock_frequency)))),	\
+		(NRFX_MHZ_TO_HZ(16)))
+
 #ifdef __cplusplus
 }
 #endif

include/zephyr/sys/util_internal.h

@@ -50,7 +50,7 @@
 #define Z_IS_ENABLED3(ignore_this, val, ...) val
 
 /* Implementation of IS_EQ(). Returns 1 if _0 and _1 are the same integer from
- * 0 to 4095, 0 otherwise.
+ * 0 to 4096, 0 otherwise.
  */
 #define Z_IS_EQ(_0, _1) Z_HAS_COMMA(Z_CAT4(Z_IS_, _0, _EQ_, _1)())