H20 batch 0

boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts

@@ -77,6 +77,8 @@
 	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
 	child-owned-channels = <3 4 7 8 9 10 11>;
 	status = "okay";
+	/delete-property/ clocks;
+	/delete-property/ clock-names;
 };
 
 &cpuapp_rram {

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi

@@ -185,8 +185,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpurad_slot0_partition: partition@66000 {
-			reg = <0x66000 DT_SIZE_K(256)>;
+		cpurad_slot0_partition: partition@54000 {
+			reg = <0x54000 DT_SIZE_K(256)>;
 		};
 	};
 
@@ -197,8 +197,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpuapp_slot0_partition: partition@a6000 {
-			reg = <0xa6000 DT_SIZE_K(248)>;
+		cpuapp_slot0_partition: partition@94000 {
+			reg = <0x94000 DT_SIZE_K(320)>;
 		};
 
 		cpuppr_code_partition: partition@e4000 {
@@ -222,7 +222,7 @@
 		};
 
 		storage_partition: partition@1e3000 {
-			reg = < 0x1e3000 DT_SIZE_K(24) >;
+			reg = < 0x1e3000 DT_SIZE_K(40) >;
 		};
 	};
 };

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-pinctrl.dtsi

@@ -98,4 +98,19 @@
 			low-power-enable;
 		};
 	};
+
+	/omit-if-no-ref/ grtc_default: grtc_default {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 1)>;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_sleep: grtc_sleep {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 1)>;
+			low-power-enable;
+		};
+	};
 };

boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi

@@ -77,4 +77,19 @@
 			low-power-enable;
 		};
 	};
+
+	/omit-if-no-ref/ grtc_default: grtc_default {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_sleep: grtc_sleep {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+			low-power-enable;
+		};
+	};
 };

drivers/clock_control/nrf_clock_calibration.c

@@ -294,3 +294,8 @@ int z_nrf_clock_calibration_skips_count(void)
 
 	return total_skips_cnt;
 }
+
+bool z_nrf_clock_calibration_is_in_progress(void)
+{
+	return cal_process_in_progress ? true : false;
+}

drivers/counter/Kconfig.nrfx

@@ -9,6 +9,12 @@ config COUNTER_NRF_RTC
 	def_bool y
 	depends on DT_HAS_NORDIC_NRF_RTC_ENABLED
 
+config COUNTER_NRFX_TIMER_USE_CLOCK_CONTROL
+	def_bool y
+	depends on $(dt_nodelabel_enabled,timer120) || \
+		 $(dt_nodelabel_enabled,timer121)
+	select CLOCK_CONTROL
+
 # Internal flag which detects if PPI wrap feature is enabled for any instance
 config COUNTER_RTC_WITH_PPI_WRAP
 	def_bool $(dt_nodelabel_bool_prop,rtc0,ppi-wrap) || \

drivers/counter/counter_nrfx_timer.c

@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/drivers/counter.h>
+#include <zephyr/drivers/clock_control/nrf_clock_control.h>
+#include <zephyr/devicetree.h>
 #include <hal/nrf_timer.h>
 #include <zephyr/sys/atomic.h>
 
@@ -32,11 +34,32 @@
 #define MAYBE_CONST_CONFIG const
 #endif
 
+#ifdef CONFIG_SOC_NRF54H20_GPD
+#include <nrf/gpd.h>
+
+#define NRF_CLOCKS_INSTANCE_IS_FAST(node)						\
+	COND_CODE_1(DT_NODE_HAS_PROP(node, power_domains),				\
+		    (IS_EQ(DT_PHA(node, power_domains, id), NRF_GPD_FAST_ACTIVE1)),	\
+		    (0))
+
+/* Macro must resolve to literal 0 or 1 */
+#define INSTANCE_IS_FAST(idx) NRF_CLOCKS_INSTANCE_IS_FAST(DT_DRV_INST(idx))
+
+#define INSTANCE_IS_FAST_OR(idx) INSTANCE_IS_FAST(idx) ||
+
+#if (DT_INST_FOREACH_STATUS_OKAY(INSTANCE_IS_FAST_OR) 0)
+#define COUNTER_ANY_FAST 1
+#endif
+#endif
+
 struct counter_nrfx_data {
 	counter_top_callback_t top_cb;
 	void *top_user_data;
 	uint32_t guard_period;
 	atomic_t cc_int_pending;
+#ifdef COUNTER_ANY_FAST
+	atomic_t active;
+#endif
 };
 
 struct counter_nrfx_ch_data {
@@ -48,6 +71,10 @@
 	struct counter_config_info info;
 	struct counter_nrfx_ch_data *ch_data;
 	NRF_TIMER_Type *timer;
+#ifdef COUNTER_ANY_FAST
+	const struct device *clk_dev;
+	struct nrf_clock_spec clk_spec;
+#endif
 	LOG_INSTANCE_PTR_DECLARE(log);
 };
 
@@ -61,6 +88,18 @@
 {
 	const struct counter_nrfx_config *config = dev->config;
 
+#ifdef COUNTER_ANY_FAST
+	struct counter_nrfx_data *data = dev->data;
+
+	if (config->clk_dev && atomic_cas(&data->active, 0, 1)) {
+		int err;
+
+		err = nrf_clock_control_request_sync(config->clk_dev, &config->clk_spec, K_FOREVER);
+		if (err < 0) {
+			return err;
+		}
+	}
+#endif
 	nrf_timer_task_trigger(config->timer, NRF_TIMER_TASK_START);
 
 	return 0;
@@ -71,6 +110,18 @@
 	const struct counter_nrfx_config *config = dev->config;
 
 	nrf_timer_task_trigger(config->timer, NRF_TIMER_TASK_STOP);
+#ifdef COUNTER_ANY_FAST
+	struct counter_nrfx_data *data = dev->data;
+
+	if (config->clk_dev && atomic_cas(&data->active, 1, 0)) {
+		int err;
+
+		err = nrf_clock_control_release(config->clk_dev, &config->clk_spec);
+		if (err < 0) {
+			return err;
+		}
+	}
+#endif
 
 	return 0;
 }
@@ -403,6 +454,20 @@
 	.set_guard_period = set_guard_period,
 };
 
+/* Get initialization level of an instance. Instances that requires clock control
+ * which is using nrfs (IPC) are initialized later.
+ */
+#define TIMER_INIT_LEVEL(idx) \
+	COND_CODE_1(INSTANCE_IS_FAST(idx), (POST_KERNEL), (PRE_KERNEL_1))
+
+/* Get initialization priority of an instance. Instances that requires clock control
+ * which is using nrfs (IPC) are initialized later.
+ */
+#define TIMER_INIT_PRIO(idx)								\
+	COND_CODE_1(INSTANCE_IS_FAST(idx),						\
+		    (UTIL_INC(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL_INIT_PRIORITY)),	\
+		    (CONFIG_COUNTER_INIT_PRIORITY))
+
 /*
  * Device instantiation is done with node labels due to HAL API
  * requirements. In particular, TIMERx_MAX_SIZE values from HALs
@@ -419,14 +484,6 @@
 			    irq_handler, DEVICE_DT_INST_GET(idx), 0))		\
 	)
 
-#if !defined(CONFIG_SOC_SERIES_BSIM_NRFXX)
-#define CHECK_MAX_FREQ(idx)									\
-		BUILD_ASSERT(DT_INST_PROP(idx, max_frequency) ==				\
-			NRF_TIMER_BASE_FREQUENCY_GET((NRF_TIMER_Type *)DT_INST_REG_ADDR(idx)))
-#else
-#define CHECK_MAX_FREQ(idx)
-#endif
-
 #define COUNTER_NRFX_TIMER_DEVICE(idx)								\
 	BUILD_ASSERT(DT_INST_PROP(idx, prescaler) <=						\
 			TIMER_PRESCALER_PRESCALER_Msk,						\
@@ -456,22 +513,29 @@
 	static MAYBE_CONST_CONFIG struct counter_nrfx_config nrfx_counter_##idx##_config = {	\
 		.info = {									\
 			.max_top_value = (uint32_t)BIT64_MASK(DT_INST_PROP(idx, max_bit_width)),\
-			.freq = DT_INST_PROP(idx, max_frequency) /				\
+			.freq = NRF_PERIPH_GET_FREQUENCY(DT_DRV_INST(idx)) /			\
 				BIT(DT_INST_PROP(idx, prescaler)),				\
 			.flags = COUNTER_CONFIG_INFO_COUNT_UP,					\
 			.channels = CC_TO_ID(DT_INST_PROP(idx, cc_num)),			\
 		},										\
 		.ch_data = counter##idx##_ch_data,						\
 		.timer = (NRF_TIMER_Type *)DT_INST_REG_ADDR(idx),				\
+		IF_ENABLED(INSTANCE_IS_FAST(idx),						\
+			(.clk_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(idx))),		\
+			 .clk_spec = {								\
+				.frequency = NRF_PERIPH_GET_FREQUENCY(DT_DRV_INST(idx)),	\
+				.accuracy = 0,							\
+				.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,		\
+				},								\
+			 ))									\
 		LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx)				\
 	};											\
-	CHECK_MAX_FREQ(idx);									\
 	DEVICE_DT_INST_DEFINE(idx,								\
 			    counter_##idx##_init,						\
 			    NULL,								\
 			    &counter_##idx##_data,						\
 			    &nrfx_counter_##idx##_config.info,					\
-			    PRE_KERNEL_1, CONFIG_COUNTER_INIT_PRIORITY,				\
+			    TIMER_INIT_LEVEL(idx), TIMER_INIT_PRIO(idx),			\
 			    &counter_nrfx_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(COUNTER_NRFX_TIMER_DEVICE)

drivers/hwinfo/hwinfo_nrf.c

@@ -8,7 +8,7 @@
 #include <zephyr/drivers/hwinfo.h>
 #include <string.h>
 #include <zephyr/sys/byteorder.h>
-#if !defined(CONFIG_SOC_SERIES_NRF54HX) && !defined(CONFIG_BOARD_QEMU_CORTEX_M0)
+#if !defined(CONFIG_BOARD_QEMU_CORTEX_M0)
 #include <helpers/nrfx_reset_reason.h>
 #endif
 
@@ -63,7 +63,7 @@
 	return length;
 }
 
-#if !defined(CONFIG_SOC_SERIES_NRF54HX) && !defined(CONFIG_BOARD_QEMU_CORTEX_M0)
+#if !defined(CONFIG_BOARD_QEMU_CORTEX_M0)
 int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
 {
 	uint32_t flags = 0;
@@ -76,16 +76,37 @@
 	if (reason & NRFX_RESET_REASON_DOG_MASK) {
 		flags |= RESET_WATCHDOG;
 	}
-	if (reason & NRFX_RESET_REASON_LOCKUP_MASK) {
+
+#if defined(NRF_RESETINFO)
+	if (reason & NRFX_RESET_REASON_LOCAL_DOG0_MASK) {
+		flags |= RESET_WATCHDOG;
+	}
+#endif
+
+#if defined(NRF_RESETINFO)
+	if ((reason & NRFX_RESET_REASON_LOCKUP)
+		|| (reason & NRFX_RESET_REASON_LOCAL_LOCKUP_MASK))
+#else
+	if (reason & NRFX_RESET_REASON_LOCKUP_MASK)
+#endif
+	{
 		flags |= RESET_CPU_LOCKUP;
 	}
+
 	if (reason & NRFX_RESET_REASON_OFF_MASK) {
 		flags |= RESET_LOW_POWER_WAKE;
 	}
 	if (reason & NRFX_RESET_REASON_DIF_MASK) {
 		flags |= RESET_DEBUG;
 	}
-	if (reason & NRFX_RESET_REASON_SREQ_MASK) {
+
+#if defined(NRF_RESETINFO)
+	if ((reason & NRFX_RESET_REASON_SREQ)
+		|| (reason & NRFX_RESET_REASON_LOCAL_SREQ_MASK))
+#else
+	if (reason & NRFX_RESET_REASON_SREQ_MASK)
+#endif
+	{
 		flags |= RESET_SOFTWARE;
 	}
 
@@ -124,11 +145,18 @@
 		flags |= RESET_DEBUG;
 	}
 #endif
+
 #if !NRF_POWER_HAS_RESETREAS
-	if (reason & NRFX_RESET_REASON_DOG1_MASK) {
+#if defined(NRF_RESETINFO)
+	if (reason & NRFX_RESET_REASON_LOCAL_DOG1_MASK)
+#else
+	if (reason & NRFX_RESET_REASON_DOG1_MASK)
+#endif
+	{
 		flags |= RESET_WATCHDOG;
 	}
-#endif
+#endif /* !NRF_POWER_HAS_RESETREAS */
+
 #if NRFX_RESET_REASON_HAS_GRTC
 	if (reason & NRFX_RESET_REASON_GRTC_MASK) {
 		flags |= RESET_CLOCK;

drivers/pinctrl/pinctrl_nrf.c

@@ -94,6 +94,15 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
 #define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
 #endif
 
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_grtc) || defined(CONFIG_NRFX_GRTC)
+#if DT_NODE_HAS_PROP(DT_NODELABEL(grtc), clkout_fast_frequency)
+#define NRF_GRTC_CLKOUT_FAST 1
+#endif
+#if DT_NODE_HAS_PROP(DT_NODELABEL(grtc), clkout_32k_frequency)
+#define NRF_GRTC_CLKOUT_SLOW 1
+#endif
+#endif
+
 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			   uintptr_t reg)
 {
@@ -336,6 +345,24 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
 			break;
 #endif /* defined(NRF_PSEL_QSPI) */
+#if defined(NRF_GRTC_CLKOUT_FAST)
+		case NRF_FUN_GRTC_CLKOUT_FAST:
+#if NRF_GPIO_HAS_SEL && defined(GPIO_PIN_CNF_CTRLSEL_GRTC)
+			nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_GRTC);
+#endif
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
+			break;
+#endif /* defined(NRF_GRTC_CLKOUT_FAST) */
+#if defined(NRF_GRTC_CLKOUT_SLOW)
+		case NRF_FUN_GRTC_CLKOUT_32K:
+#if NRF_GPIO_HAS_SEL && defined(GPIO_PIN_CNF_CTRLSEL_GRTC)
+			nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_GRTC);
+#endif
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
+			break;
+#endif /* defined(NRF_GRTC_CLKOUT_SLOW) */
 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can)
 		/* Pin routing is controlled by secure domain, via UICR */
 		case NRF_FUN_CAN_TX:

drivers/power_domain/Kconfig

@@ -60,6 +60,7 @@ config POWER_DOMAIN_GPIO_MONITOR
 	default y
 	depends on DT_HAS_POWER_DOMAIN_GPIO_MONITOR_ENABLED
 	depends on GPIO
+	depends on PM_DEVICE
 	select DEVICE_DEPS
 
 if POWER_DOMAIN_GPIO_MONITOR

drivers/power_domain/power_domain_gpio_monitor.c

@@ -39,7 +39,7 @@ static int pd_on_domain_visitor(const struct device *dev, void *context)
 		return 0;
 	}
 
-	dev->pm->usage = 0;
+	dev->pm->base.usage = 0;
 	(void)pm_device_action_run(dev, visitor_context->action);
 	return 0;
 }