draft: vpr various fixes #2425
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draft: vpr various fixes #2425
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The tp register has been remove from the common RISC-V stack frame so remove it from the VPR specific variant declared via SOC_ISR_STACKING_ESF_DECLARE. This saves 4 bytes and allows removing a lot of padding to get the 16B aligned size. Signed-off-by: Karsten Koenig <[email protected]>
EngB+ uses 32bit bus-width stacking sequence for all VPR cores. Signed-off-by: Karsten Koenig <[email protected]>
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done in different pr |
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