[Backport v3.7.99-ncs3-branch] [nrf fromtree] drivers: udc_dwc2: Rework control endpoint feeding #2478
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The DOEPTSIZ0 XferSize field is 7 bits long, meaning that maximum single transfer can be 127 bytes long. Configure the control write (OUT) transfers considering the XferSize field size to support transfers with data stage larger than 127 bytes. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit 18be1d0) (cherry picked from commit 817a6d2)
Prepare buffer to receive SETUP data on OUT endpoint 0 after endpoint halt. This solves the issue where the device would no longer process any control transfers after the first failed transfer with too large OUT Data Stage (when processing failed due to data stage buffer allocation failure). Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit 883b77f) (cherry picked from commit 82c286d)
DMA transfers are supposed to write to buffer tail. Use the proper pointer to make multipart DMA transfers actually write the data to the intended location. The issue was observed on control write transfers where the OUT Data Stage was at least 128 bytes (because endpoint 0 transfer width is limited to 7 bits). The issue is unlikely to happen on non-control transfers because the transfer size width is at least 11 bits (at most 19 bits) and packet size counter is at least 4 bits (at most: 10 bits) which means that at least 2048 byte transfer spanning at least 15 packets (or at least 524288 byte spanning 1023 packets for 19 bits transfer size counter and 10 bits packet counter) is required to necessitate multipart DMA. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit 45ee2a0) (cherry picked from commit 3d948a5)
Use helper functions to check whether device is operating in Buffer DMA or Completer mode. This allows compile time optimizations to remove DMA handling code when DMA is disabled via KConfig symbol UDC_DWC2_DMA. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit d4cc8de) (cherry picked from commit a284c39)
Control OUT buffers must be multiple of bMaxPacketSize0 in Buffer DMA mode. While the transfer can be configured to smaller values, DMA will write data past the buffer (and transfer size counter will underflow) if the packet on the bus is larger or if there are multiple back-to-back SETUP packets. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit a61afc8) (cherry picked from commit 5ee4d80)
The transfer is finished after ZLP is transmitted. Do not re-enable the endpoint waiting for more data. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit ea72b27) (cherry picked from commit a82f2fc)
In Completer mode SETUP data can always be received and therefore endpoint 0 should only be enabled for OUT Data Stage and OUT Status Stage. In Buffer DMA mode, SETUP can only be received when endpoint is enabled and therefore the software has to make sure that there is a buffer available to receive SETUP data. Rework the EP0 buffer feeding to adhere to DWC2 Programming Guide. Synchronize the accesses with driver mutex to avoid interrupt related race conditions. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit 8348d9a) (cherry picked from commit d0bef36)
nordicjm
approved these changes
Feb 10, 2025
jfischer-no
approved these changes
Feb 11, 2025
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Backport d0bef36~7..d0bef36 from #2474.