[nrf fromlist] Add support for nRF54L20 FLPR core

boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk

@@ -3,3 +3,4 @@
 
 config BOARD_NRF54L20PDK
 	select SOC_NRF54L20_ENGA_CPUAPP if BOARD_NRF54L20PDK_NRF54L20_CPUAPP
+	select SOC_NRF54L20_ENGA_CPUFLPR if BOARD_NRF54L20PDK_NRF54L20_CPUFLPR

boards/nordic/nrf54l20pdk/board.cmake

@@ -1,7 +1,11 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
+if(CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUAPP)
+  board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
+elseif(CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUFLPR)
+  board_runner_args(jlink "--speed=4000")
+endif()
 
 include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nordic/nrf54l20pdk/board.yml

@@ -4,3 +4,6 @@ board:
   vendor: nordic
   socs:
   - name: nrf54l20
+    variants:
+    - name: xip
+      cpucluster: cpuflpr

boards/nordic/nrf54l20pdk/doc/index.rst

@@ -65,6 +65,12 @@ built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
 building and running.
 
+Applications for the ``nrf54l20pdk/nrf54l20/cpuflpr`` board target need
+to be built using sysbuild to include the ``vpr_launcher`` image for the application core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core::
+ west build -p -b nrf54l20pdk/nrf54l20/cpuflpr --sysbuild
+
 Flashing
 ========
 

boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi

@@ -27,11 +27,6 @@
 	status = "okay";
 };
 
-&hfpll {
-	/* For now use 64 MHz clock for CPU and fast peripherals. */
-	clock-frequency = <DT_FREQ_M(64)>;
-};
-
 &lfxo {
 	load-capacitors = "internal";
 	load-capacitance-femtofarad = <15500>;

boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi

@@ -91,3 +91,15 @@
 	pinctrl-1 = <&pwm20_sleep>;
 	pinctrl-names = "default", "sleep";
 };
+
+&uart30 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&hfpll {
+	/* For now use 64 MHz clock for CPU and fast peripherals. */
+	clock-frequency = <DT_FREQ_M(64)>;
+};

boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi

@@ -34,4 +34,27 @@
 			low-power-enable;
 		};
 	};
+
+	/omit-if-no-ref/ uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			low-power-enable;
+		};
+	};
 };

boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.dts

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf54l20_enga_cpuflpr.dtsi>
+#include "nrf54l20pdk_nrf54l20-common.dtsi"
+
+/ {
+	model = "Nordic nRF54L20 PDK nRF54L20 FLPR MCU";
+	compatible = "nordic,nrf54l20pdk_nrf54l20-cpuflpr";
+
+	chosen {
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+		zephyr,code-partition = &cpuflpr_code_partition;
+		zephyr,flash = &cpuflpr_rram;
+		zephyr,sram = &cpuflpr_sram;
+	};
+};
+
+&cpuflpr_sram {
+	status = "okay";
+};
+
+&cpuflpr_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuflpr_code_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+	};
+};
+
+&grtc {
+	owned-channels = <3 4>;
+	status = "okay";
+};
+
+&uart30 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};

boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml

@@ -0,0 +1,14 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: nrf54l20pdk/nrf54l20/cpuflpr
+name: nRF54L20-PDK-nRF54L20-Fast-Lightweight-Peripheral-Processor
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+ram: 64
+flash: 64
+supported:
+  - counter
+  - gpio

boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig

@@ -0,0 +1,19 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Execute from SRAM
+CONFIG_XIP=n
+
+CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL=y

dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi

@@ -10,6 +10,11 @@ cpu: &cpuapp {};
 systick: &cpuapp_systick {};
 nvic: &cpuapp_nvic {};
 
+/delete-node/ &cpuflpr;
+/delete-node/ &cpuflpr_rram;
+/delete-node/ &cpuflpr_sram;
+/delete-node/ &cpuflpr_clic;
+
 / {
 	chosen {
 		zephyr,entropy = &prng;
@@ -32,6 +37,27 @@ nvic: &cpuapp_nvic {};
 	};
 };
 
+&cpuflpr_vpr {
+	cpuapp_vevif_rx: mailbox@1 {
+		compatible = "nordic,nrf-vevif-event-rx";
+		reg = <0x0 0x1000>;
+		status = "disabled";
+		interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>;
+		#mbox-cells = <1>;
+		nordic,events = <1>;
+		nordic,events-mask = <0x00100000>;
+	};
+
+	cpuapp_vevif_tx: mailbox@0 {
+		compatible = "nordic,nrf-vevif-task-tx";
+		reg = <0x0 0x1000>;
+		#mbox-cells = <1>;
+		nordic,tasks = <7>;
+		nordic,tasks-mask = <0x007f0000>;
+		status = "disabled";
+	};
+};
+
 &cpuapp_ppb {
 	compatible = "simple-bus";
 	ranges;

dts/common/nordic/nrf54l20.dtsi

@@ -11,6 +11,10 @@
 
 /delete-node/ &sw_pwm;
 
+/* Domain IDs. Can be used to specify channel links in IPCT nodes. */
+#define NRF_DOMAIN_ID_APPLICATION 0
+#define NRF_DOMAIN_ID_FLPR 1
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -32,6 +36,14 @@
 				swo-ref-frequency = <DT_FREQ_M(128)>;
 			};
 		};
+
+		cpuflpr: cpu@1 {
+			compatible = "nordic,vpr";
+			reg = <1>;
+			device_type = "cpu";
+			riscv,isa = "rv32emc";
+			nordic,bus-width = <64>;
+		};
 	};
 
 	clocks {
@@ -77,10 +89,18 @@
 
 		cpuapp_sram: memory@20000000 {
 			compatible = "mmio-sram";
-			reg = <0x20000000 DT_SIZE_K(511)>;
+			reg = <0x20000000 DT_SIZE_K(447)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x20000000 0x6fc00>;
+		};
+
+		cpuflpr_sram: memory@2006fc00 {
+			compatible = "mmio-sram";
+			reg = <0x2006fc00 DT_SIZE_K(64)>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x0 0x20000000 0x7fc00>;
+			ranges = <0x0 0x2006fc00 0x10000>;
 		};
 
 		global_peripherals: peripheral@50000000 {
@@ -106,6 +126,24 @@
 				status = "disabled";
 			};
 
+			cpuflpr_vpr: vpr@4c000 {
+				compatible = "nordic,nrf-vpr-coprocessor";
+				reg = <0x4c000 0x1000>;
+				ranges = <0x0 0x4c000 0x1000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				status = "disabled";
+
+				cpuflpr_clic: interrupt-controller@f0000000 {
+					compatible = "nordic,nrf-clic";
+					reg = <0xf0000000 0x143c>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					#address-cells = <1>;
+					status = "disabled";
+				};
+			};
+
 			spi00: spi@4d000 {
 				/*
 				 * This spi node can be either SPIM or SPIS,
@@ -737,7 +775,14 @@
 
 			cpuapp_rram: rram@0 {
 				compatible = "soc-nv-flash";
-				reg = <0x0 DT_SIZE_K(2028)>;
+				reg = <0x0 DT_SIZE_K(1972)>;
+				erase-block-size = <4096>;
+				write-block-size = <16>;
+			};
+
+			cpuflpr_rram: rram@1ed000 {
+				compatible = "soc-nv-flash";
+				reg = <0x1ed000 DT_SIZE_K(64)>;
 				erase-block-size = <4096>;
 				write-block-size = <16>;
 			};

dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nordic/nrf54l20.dtsi>
+
+cpu: &cpuflpr {};
+clic: &cpuflpr_clic {};
+
+/delete-node/ &cpuapp;
+/delete-node/ &cpuapp_rram;
+/delete-node/ &cpuapp_ppb;
+/delete-node/ &cpuapp_sram;
+
+/ {
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&cpuflpr_clic>;
+		ranges;
+	};
+};
+
+&cpuflpr {
+	cpuflpr_vevif_rx: mailbox {
+		compatible = "nordic,nrf-vevif-task-rx";
+		status = "disabled";
+		interrupt-parent = <&cpuflpr_clic>;
+		interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <17 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <18 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <19 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <20 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <21 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <22 NRF_DEFAULT_IRQ_PRIORITY>;
+		#mbox-cells = <1>;
+		nordic,tasks = <7>;
+		nordic,tasks-mask = <0x007f0000>;
+	};
+};
+
+&cpuflpr_vpr {
+	cpuflpr_vevif_tx: mailbox {
+		compatible = "nordic,nrf-vevif-event-tx";
+		#mbox-cells = <1>;
+		nordic,events = <1>;
+		nordic,events-mask = <0x00100000>;
+		status = "disabled";
+	};
+};
+
+&cpuflpr_clic {
+	status = "okay";
+};
+
+&grtc {
+	interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
+};
+
+&gpiote20 {
+	interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>;
+};
+
+&gpiote30 {
+	interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>;
+};