Skip to content

[nrf fromlist] boards: nordic: nrf54l20pdk: Increase RAM,Flash on FLPR #2629

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
wants to merge 1 commit into from
+21 −17
Closed

[nrf fromlist] boards: nordic: nrf54l20pdk: Increase RAM,Flash on FLPR #2629

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ toolchain:
- xtools
- zephyr
sysbuild: true
ram: 512
ram: 415
Copy link
Contributor Author

@nordic-segl nordic-segl Mar 27, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

main branch without FLPR snippet: 512k - 64k -1k = 447k
if FLPR gets 96k: 512k - 96k - 1k = 415k

flash: 449
supported:
- adc
Expand Down
2 changes: 1 addition & 1 deletion boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@

cpuflpr_code_partition: partition@0 {
label = "image-0";
reg = <0x0 DT_SIZE_K(64)>;
reg = <0x0 DT_SIZE_K(96)>;
};
};
};
Expand Down
6 changes: 4 additions & 2 deletions boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,10 @@ arch: riscv
toolchain:
- zephyr
sysbuild: true
ram: 64
flash: 64
ram: 96
flash: 96
supported:
- counter
- gpio
- i2c
- spi
18 changes: 10 additions & 8 deletions dts/common/nordic/nrf54l20.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -95,20 +95,22 @@

cpuapp_sram: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(447)>;
reg = <0x20000000 DT_SIZE_K(415)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20000000 0x6fc00>;
ranges = <0x0 0x20000000 0x67c00>;
};

cpuflpr_sram: memory@2006fc00 {
cpuflpr_sram: memory@20067c00 {
compatible = "mmio-sram";
reg = <0x2006fc00 DT_SIZE_K(64)>;
reg = <0x20067c00 DT_SIZE_K(96)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2006fc00 0x10000>;
ranges = <0x0 0x20067c00 0x18000>;
};

/* 0x20067c00 - 0x20080000; size 0x400 (1k): Reserved for VPR context */
Copy link
Contributor Author

@nordic-segl nordic-segl Mar 27, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

typo:
/* 0x2007fc00 - 0x20080000; size 0x400 (1k): Reserved for VPR context */


global_peripherals: peripheral@50000000 {
ranges = <0x0 0x50000000 0x10000000>;
#address-cells = <1>;
Expand Down Expand Up @@ -805,14 +807,14 @@

cpuapp_rram: rram@0 {
compatible = "soc-nv-flash";
reg = <0x0 DT_SIZE_K(1972)>;
reg = <0x0 DT_SIZE_K(1940)>;
erase-block-size = <4096>;
write-block-size = <16>;
};

cpuflpr_rram: rram@1ed000 {
cpuflpr_rram: rram@1e5000 {
compatible = "soc-nv-flash";
reg = <0x1ed000 DT_SIZE_K(64)>;
reg = <0x1e5000 DT_SIZE_K(96)>;
erase-block-size = <4096>;
write-block-size = <16>;
};
Expand Down
10 changes: 5 additions & 5 deletions snippets/nordic-flpr/soc/nrf54l20_cpuapp.overlay
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,18 +9,18 @@
#address-cells = <1>;
#size-cells = <1>;

cpuflpr_code_partition: image@1ed000 {
cpuflpr_code_partition: image@1e5000 {
/* FLPR core code partition */
reg = <0x1ed000 DT_SIZE_K(64)>;
reg = <0x1e5000 DT_SIZE_K(96)>;
};
};

cpuflpr_sram_code_data: memory@2006fc00 {
cpuflpr_sram_code_data: memory@20067c00 {
compatible = "mmio-sram";
reg = <0x2006fc00 DT_SIZE_K(64)>;
reg = <0x20067c00 DT_SIZE_K(96)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2006fc00 0x10000>;
ranges = <0x0 0x20067c00 0x18000>;
};
};
};
Expand Down