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[nrf fromtree][nrf noup] Changes needed for MSPI shim driver for sQSPI #2711

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Merged
merged 3 commits into from
Apr 9, 2025
Merged

[nrf fromtree][nrf noup] Changes needed for MSPI shim driver for sQSPI #2711

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9931618
[nrf fromtree] dts: bindings: nrf-vpr: Allow specifying pins and not …
anangl Mar 28, 2025
1c50ab0
[nrf fromtree] soc: nordic: Disable cache for soft peripheral RAM reg…
anangl Apr 4, 2025
67a4220
[nrf noup] drivers: pinctrl_nrf: Extend handling of SDP MSPI pins
anangl Apr 4, 2025
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3 changes: 2 additions & 1 deletion drivers/misc/nordic_vpr_launcher/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,8 @@
config NORDIC_VPR_LAUNCHER
bool "Nordic VPR coprocessor launcher"
default y
depends on DT_HAS_NORDIC_NRF_VPR_COPROCESSOR_ENABLED
depends on DT_HAS_NORDIC_NRF_VPR_COPROCESSOR_ENABLED && \
$(dt_compat_any_has_prop,$(DT_COMPAT_NORDIC_NRF_VPR_COPROCESSOR),execution-memory)
help
When enabled, the VPR coprocessors will be automatically launched
during system initialization.
Expand Down
15 changes: 12 additions & 3 deletions drivers/misc/nordic_vpr_launcher/nordic_vpr_launcher.c
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,11 @@ static int nordic_vpr_launcher_init(const struct device *dev)
{
const struct nordic_vpr_launcher_config *config = dev->config;

/* Do nothing if execution memory is not specified for a given VPR. */
if (config->exec_addr == 0) {
return 0;
}

#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(source_memory)
if (config->size > 0U) {
LOG_DBG("Loading VPR (%p) from %p to %p (%zu bytes)", config->vpr,
Expand Down Expand Up @@ -63,16 +68,20 @@ static int nordic_vpr_launcher_init(const struct device *dev)
(DT_REG_ADDR(node_id) + \
COND_CODE_0(DT_FIXED_PARTITION_EXISTS(node_id), (0), (DT_REG_ADDR(DT_GPARENT(node_id)))))

#define NEEDS_COPYING(inst) UTIL_AND(DT_INST_NODE_HAS_PROP(inst, execution_memory), \
DT_INST_NODE_HAS_PROP(inst, source_memory))

#define NORDIC_VPR_LAUNCHER_DEFINE(inst) \
IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, source_memory), \
IF_ENABLED(NEEDS_COPYING(inst), \
(BUILD_ASSERT((DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)) <= \
DT_REG_SIZE(DT_INST_PHANDLE(inst, source_memory))), \
"Execution memory exceeds source memory size");)) \
\
static const struct nordic_vpr_launcher_config config##inst = { \
.vpr = (NRF_VPR_Type *)DT_INST_REG_ADDR(inst), \
.exec_addr = VPR_ADDR(DT_INST_PHANDLE(inst, execution_memory)), \
IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, source_memory), \
IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, execution_memory), \
(.exec_addr = VPR_ADDR(DT_INST_PHANDLE(inst, execution_memory)),)) \
IF_ENABLED(NEEDS_COPYING(inst), \
(.src_addr = VPR_ADDR(DT_INST_PHANDLE(inst, source_memory)), \
.size = DT_REG_SIZE(DT_INST_PHANDLE(inst, execution_memory)),))}; \
\
Expand Down
19 changes: 11 additions & 8 deletions drivers/pinctrl/pinctrl_nrf.c
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Original file line number Diff line number Diff line change
Expand Up @@ -112,12 +112,17 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
#define NRF_PSEL_TDM(reg, line) ((NRF_TDM_Type *)reg)->PSEL.line
#endif

#if defined(CONFIG_SOC_NRF54L15_CPUAPP)
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || defined(CONFIG_MSPI_NRFE)
#define NRF_PSEL_SDP_MSPI(psel) \
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || \
defined(CONFIG_MSPI_NRFE) || \
DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(nordic_nrf_vpr_coprocessor, pinctrl_0)
#if defined(CONFIG_SOC_SERIES_NRF54LX)
#define NRF_PSEL_SDP_MSPI(psel) \
nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR);
#elif defined(CONFIG_SOC_SERIES_NRF54HX)
/* On nRF54H, pin routing is controlled by secure domain, via UICR. */
#define NRF_PSEL_SDP_MSPI(psel)
#endif
#endif
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || ... */

int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
Expand Down Expand Up @@ -472,8 +477,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
#endif /* defined(NRF_PSEL_TWIS) */
#if defined(CONFIG_SOC_NRF54L15_CPUAPP)
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller)
#if defined(NRF_PSEL_SDP_MSPI)
case NRF_FUN_SDP_MSPI_CS0:
case NRF_FUN_SDP_MSPI_CS1:
case NRF_FUN_SDP_MSPI_CS2:
Expand All @@ -492,8 +496,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
break;
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) */
#endif /* CONFIG_SOC_NRF54L15_CPUAPP */
#endif /* defined(NRF_PSEL_SDP_MSPI) */
default:
return -ENOTSUP;
}
Expand Down
9 changes: 6 additions & 3 deletions dts/bindings/riscv/nordic,nrf-vpr-coprocessor.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -9,14 +9,17 @@ description: |
VPR is a RISC-V CPU implementation. VPR instances are exposed to other CPUs as
peripherals.

include: base.yaml
include: [base.yaml, pinctrl-device.yaml]

properties:
execution-memory:
type: phandle
required: true
description: |
Memory area from which the VPR core will execute.
Memory area from which the VPR code will execute.
If not specified, the VPR coprocessor will not be launched automatically
by the nordic_vpr_launcher driver when the node is enabled. In such case,
the launching is supposed to be done explicitly by the user code, in some
custom way presumably.

source-memory:
type: phandle
Expand Down
7 changes: 7 additions & 0 deletions soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,9 @@
#define CAN121_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), message_ram) + \
DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), m_can)

#define SOFTPERIPH_BASE DT_REG_ADDR(DT_NODELABEL(softperiph_ram))
#define SOFTPERIPH_SIZE DT_REG_SIZE(DT_NODELABEL(softperiph_ram))

static struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
Expand All @@ -40,6 +43,10 @@ static struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("CAN121_MCAN", CAN121_BASE,
REGION_RAM_NOCACHE_ATTR(CAN121_BASE, CAN121_SIZE)),
#endif
#if DT_NODE_EXISTS(DT_NODELABEL(softperiph_ram))
MPU_REGION_ENTRY("SOFTPERIPH_RAM", SOFTPERIPH_BASE,
REGION_RAM_NOCACHE_ATTR(SOFTPERIPH_BASE, SOFTPERIPH_SIZE)),
#endif
};

const struct arm_mpu_config mpu_config = {
Expand Down