[nrf fromlist] soc: add ironside boot report

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron.dts

@@ -9,6 +9,12 @@
 /delete-node/&cpurad_rx_partitions;
 /delete-node/&cpuapp_rx_partitions;
 
+/* Update the location of cpusys IPC shared memory */
+/delete-node/&cpuapp_cpusys_ipc_shm;
+/delete-node/&cpusys_cpuapp_ipc_shm;
+/delete-node/&cpurad_cpusys_ipc_shm;
+/delete-node/&cpusys_cpurad_ipc_shm;
+
 /* This is not yet an exhaustive memory map, and contain only a minimum required to boot
  * the application core.
  */
@@ -34,20 +40,48 @@
 
 		slot0_partition: partition@3c000 {
 			label = "image-0";
-			reg = <0x3c000 DT_SIZE_K(200)>;
+			reg = <0x3c000 DT_SIZE_K(336)>;
 		};
 
-		slot1_partition: partition@6E000 {
+		slot1_partition: partition@90000 {
 			label = "image-1";
-			reg = <0x6E000 DT_SIZE_K(200)>;
+			reg = <0x90000 DT_SIZE_K(336)>;
+		};
+
+		cpuppr_code_partition: partition@e4000 {
+			reg = <0xe4000 DT_SIZE_K(64)>;
+		};
+
+		cpuflpr_code_partition: partition@f4000 {
+			reg = <0xf4000 DT_SIZE_K(48)>;
+		};
+	};
+};
+
+/ {
+	reserved-memory {
+		sysctrl_rom_report: memory@2f88ff00 {
+			reg = <0x2f88ff00 0x100>;
+		};
+
+		cpuapp_ironside_se_boot_report: memory@2f88fd00 {
+			reg = <0x2f88fd00 0x200>;
+		};
+
+		cpusys_cpurad_ipc_shm: memory@2f88f780 {
+			reg = <0x2f88f780 0x80>;
+		};
+
+		cpurad_cpusys_ipc_shm: memory@2f88f700 {
+			reg = <0x2f88f700 0x80>;
 		};
 
-		cpuppr_code_partition: partition@a4000 {
-			reg = <0xa4000 DT_SIZE_K(64)>;
+		cpusys_cpuapp_ipc_shm: memory@2f88f680 {
+			reg = <0x2f88f680 0x80>;
 		};
 
-		cpuflpr_code_partition: partition@b4000 {
-			reg = <0xb4000 DT_SIZE_K(48)>;
+		cpuapp_cpusys_ipc_shm: memory@2f88f600 {
+			reg = <0x2f88f600 0x80>;
 		};
 	};
 };

soc/nordic/nrf54h/CMakeLists.txt

@@ -18,3 +18,4 @@ zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld)
 
 add_subdirectory(bicr)
 add_subdirectory(gpd)
+add_subdirectory(ironside/se)

soc/nordic/nrf54h/Kconfig

@@ -72,8 +72,9 @@ config SOC_NRF54H20_CPUPPR
 config SOC_NRF54H20_CPUFLPR
 	select RISCV_CORE_NORDIC_VPR
 
-rsource "bicr/Kconfig"
-rsource "gpd/Kconfig"
-
 config SOC_NRF54H20_IRON
 	select EXPERIMENTAL if MCUBOOT
+
+rsource "bicr/Kconfig"
+rsource "gpd/Kconfig"
+rsource "ironside/se/Kconfig"

soc/nordic/nrf54h/ironside/se/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_SOC_NRF54H20_IRONSIDE_SE_BOOT_REPORT ironside_se_boot_report.c)
+zephyr_include_directories(include)

soc/nordic/nrf54h/ironside/se/Kconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_NRF54H20_IRONSIDE_SE_BOOT_REPORT
+	bool "Nordic IRONside SE boot report"
+	default y if SOC_NRF54H20_CPUAPP
+	depends on SOC_NRF54H20_IRON
+	help
+	  This option enables parsing of the Boot Report populated by Nordic IRONside SE.
+
+config SOC_NRF54H20_IRONSIDE_SE_BOOT_REPORT_MAGIC
+	hex
+	default 0x4d69546f
+	help
+	  Constant used to check if an Nordic IRONside SE boot report has been written.

soc/nordic/nrf54h/ironside/se/include/nrf/ironside_se_boot_report.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_NORDIC_NRF54H_IRONSIDE_SE_BOOT_REPORT_INCLUDE_NRF_IRONSIDE_SE_BOOT_REPORT_H_
+#define ZEPHYR_SOC_NORDIC_NRF54H_IRONSIDE_SE_BOOT_REPORT_INCLUDE_NRF_IRONSIDE_SE_BOOT_REPORT_H_
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define IRONSIDE_SE_BOOT_REPORT_LOCAL_DOMAIN_CONTEXT_SIZE (16UL) /* Size in bytes */
+#define IRONSIDE_SE_BOOT_REPORT_RANDOM_DATA_SIZE (32UL) /* Size in bytes */
+
+/** @brief UICR error description contained in the boot report. */
+struct ironside_se_boot_report_uicr_error {
+	/** The type of error. A value of 0 indicates no error */
+	uint32_t error_type;
+	/** Error descriptions specific to each type of UICR error */
+	union {
+		/** RFU */
+		struct {
+			uint32_t rfu[4];
+		} rfu;
+	} description;
+};
+
+/** @brief IRONside boot report. */
+struct ironside_se_boot_report {
+	/** Magic value used to identify valid boot report */
+	uint32_t magic;
+	/** Firmware version of IRONside SE. 8bit MAJOR.MINOR.PATCH.SEQNUM */
+	uint32_t ironside_se_version_int;
+	/** Human readable extraversion of IRONside SE */
+	char ironside_se_extraversion[12];
+	/** Firmware version of IRONside SE recovery firmware. 8bit MAJOR.MINOR.PATCH.SEQNUM */
+	uint32_t ironside_se_recovery_version_int;
+	/** Human readable extraversion of IRONside SE recovery firmware */
+	char ironside_se_recovery_extraversion[12];
+	/** Copy of SICR.UROT.UPDATE.STATUS.*/
+	uint32_t ironside_update_status;
+	/** See @ref ironside_se_boot_report_uicr_error */
+	struct ironside_se_boot_report_uicr_error uicr_error_description;
+	/** Data passed from booting local domain to local domain being booted */
+	uint8_t local_domain_context[IRONSIDE_SE_BOOT_REPORT_LOCAL_DOMAIN_CONTEXT_SIZE];
+	/** CSPRNG data */
+	uint8_t random_data[IRONSIDE_SE_BOOT_REPORT_RANDOM_DATA_SIZE];
+	/** Reserved for Future Use */
+	uint32_t rfu[64];
+};
+
+/**
+ * @brief Get a pointer to the IRONside boot report.
+ *
+ * @param[out] report Will be set to point to the IRONside boot report.
+ *
+ * @return non-negative value if success, negative value otherwise.
+ * @retval -EFAULT if the magic field in the report is incorrect.
+ * @retval -EINVAL if @ref report is NULL.
+ */
+int ironside_se_boot_report_get(const struct ironside_se_boot_report **report);
+
+#endif /* ZEPHYR_SOC_NORDIC_NRF54H_IRONSIDE_SE_BOOT_REPORT_INCLUDE_NRF_IRONSIDE_SE_BOOT_REPORT_H_ */

soc/nordic/nrf54h/ironside/se/ironside_se_boot_report.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <zephyr/devicetree.h>
+#include <nrf/ironside_se_boot_report.h>
+
+#define IRONSIDE_SE_BOOT_REPORT_ADDR  DT_REG_ADDR(DT_NODELABEL(cpuapp_ironside_se_boot_report))
+#define IRONSIDE_SE_BOOT_REPORT_MAGIC CONFIG_SOC_NRF54H20_IRONSIDE_SE_BOOT_REPORT_MAGIC
+
+int ironside_se_boot_report_get(const struct ironside_se_boot_report **report)
+{
+	const struct ironside_se_boot_report *tmp_report =
+		(const struct ironside_se_boot_report *)IRONSIDE_SE_BOOT_REPORT_ADDR;
+
+	if (tmp_report->magic != IRONSIDE_SE_BOOT_REPORT_MAGIC) {
+		return -EINVAL;
+	}
+
+	*report = tmp_report;
+
+	return 0;
+}

tests/boards/nrf/ironside_se_boot_report/CMakeLists.txt

@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(ironside_se_boot_report)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})

tests/boards/nrf/ironside_se_boot_report/prj.conf

@@ -0,0 +1 @@
+# Empty

tests/boards/nrf/ironside_se_boot_report/src/main.c

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nrf/ironside_se_boot_report.h>
+#include <stdio.h>
+
+int main(void)
+{
+	int err;
+	const struct ironside_se_boot_report *report;
+
+	err = ironside_se_boot_report_get(&report);
+	printf("err:  %d\n", err);
+	printf("version: 0x%x\n", report->ironside_se_version_int);
+	printf("extraversion: %s\n", report->ironside_se_extraversion);
+
+	return 0;
+}

tests/boards/nrf/ironside_se_boot_report/testcase.yaml

@@ -0,0 +1,19 @@
+common:
+  tags:
+    - drivers
+    - hwinfo
+  harness: console
+
+tests:
+  soc.nordic.ironside_se_boot_report:
+    harness_config:
+      type: multi_line
+      ordered: true
+      regex:
+        - "err: 0"
+        - "version: 0x([0-9a-fA-F]+)"
+        - "extraversion: ([0-9a-fA-F]+)"
+    platform_allow:
+      - nrf54h20dk/nrf54h20/cpuapp/iron
+    integration_platforms:
+      - nrf54h20dk/nrf54h20/cpuapp/iron