Replace SDFW with IronSide SE

boards/nordic/nrf54h20dk/Kconfig.defconfig

@@ -9,28 +9,33 @@ config BT_HCI_IPC
 config MAX_THREAD_BYTES
 	default 3 if USERSPACE
 
-endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
 
-if BOARD_NRF54H20DK_NRF54H20_CPURAD
+if !USE_DT_CODE_PARTITION
 
-config MAX_THREAD_BYTES
-	default 3 if USERSPACE
+# Application core firmware must start at this offset when not using MCUboot.
+# However, the default 'zephyr,code-partition' in DT is set for MCUboot.
+config FLASH_LOAD_OFFSET
+	default $(dt_nodelabel_reg_addr_hex,cpuapp_boot_partition)
 
-endif # BOARD_NRF54H20DK_NRF54H20_CPURAD
+# This is meant to span 'cpuapp_boot_partition' and 'cpuapp_slot0_partition'
+# in the default memory map.
+config FLASH_LOAD_SIZE
+	default $(add_hex, $(dt_nodelabel_reg_addr_hex,cpuapp_slot0_partition), \
+			   $(dt_nodelabel_reg_size_hex,cpuapp_slot0_partition), \
+			   -$(dt_nodelabel_reg_addr_hex,cpuapp_boot_partition))
 
-if BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON
+endif # !USE_DT_CODE_PARTITION
 
-config ROM_START_OFFSET
-	default 0x800 if BOOTLOADER_MCUBOOT
-
-config FLASH_LOAD_OFFSET
-	default 0x30000 if !USE_DT_CODE_PARTITION
+endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP
 
-endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON
+if BOARD_NRF54H20DK_NRF54H20_CPURAD
 
-if BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON
+config MAX_THREAD_BYTES
+	default 3 if USERSPACE
 
 config ROM_START_OFFSET
 	default 0x800 if BOOTLOADER_MCUBOOT
 
-endif # BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON
+endif # BOARD_NRF54H20DK_NRF54H20_CPURAD

boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk

@@ -2,13 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_NRF54H20DK
-	select SOC_NRF54H20_CPUAPP if (BOARD_NRF54H20DK_NRF54H20_CPUAPP || \
-				       BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON)
-	select SOC_NRF54H20_CPURAD if (BOARD_NRF54H20DK_NRF54H20_CPURAD || \
-				       BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON)
+	select SOC_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP
+	select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD
 	select SOC_NRF54H20_CPUPPR if (BOARD_NRF54H20DK_NRF54H20_CPUPPR || \
 				       BOARD_NRF54H20DK_NRF54H20_CPUPPR_XIP)
 	select SOC_NRF54H20_CPUFLPR if (BOARD_NRF54H20DK_NRF54H20_CPUFLPR || \
 				        BOARD_NRF54H20DK_NRF54H20_CPUFLPR_XIP)
-	select SOC_NRF54H20_IRON if (BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON || \
-				       BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON)

boards/nordic/nrf54h20dk/Kconfig.sysbuild

@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NRF54H20DK_NRF54H20_CPURAD
+
+config NRF_DEFAULT_EMPTY
+	default y
+
+endif # BOARD_NRF54H20DK_NRF54H20_CPURAD

boards/nordic/nrf54h20dk/board.cmake

@@ -2,10 +2,7 @@
 
 include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
 
-if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
-   CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD OR
-   CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON OR
-   CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON)
+if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD)
   if(CONFIG_SOC_NRF54H20_CPUAPP)
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuapp.JLinkScript)
   else()
@@ -17,7 +14,7 @@ if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
 endif()
 
 if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUFLPR)
-  if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR)
+  if(CONFIG_SOC_NRF54H20_CPUPPR)
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuppr.JLinkScript)
   else()
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuflpr.JLinkScript)

boards/nordic/nrf54h20dk/board.yml

@@ -9,10 +9,6 @@ board:
       cpucluster: cpuppr
     - name: xip
       cpucluster: cpuflpr
-    - name: iron
-      cpucluster: cpuapp
-    - name: iron
-      cpucluster: cpurad
   revision:
     format: major.minor.patch
     default: "0.9.0"

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi

@@ -7,17 +7,17 @@
 / {
 	ipc {
 		cpusec_cpuapp_ipc: ipc-1-2 {
-			compatible = "zephyr,ipc-icmsg";
+			compatible = "nordic,ironside-call";
 			status = "disabled";
-			dcache-alignment = <32>;
+			memory-region = <&cpusec_cpuapp_ipc_shm>;
 			mboxes = <&cpusec_bellboard 12>,
 				 <&cpuapp_bellboard 0>;
 		};
 
 		cpusec_cpurad_ipc: ipc-1-3 {
-			compatible = "zephyr,ipc-icmsg";
+			compatible = "nordic,ironside-call";
 			status = "disabled";
-			dcache-alignment = <32>;
+			memory-region = <&cpusec_cpurad_ipc_shm>;
 			mboxes = <&cpusec_bellboard 18>,
 				 <&cpurad_bellboard 0>;
 		};