[nrf fromtree] A few QSPI and MSPI related changes #2984
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… XIP users Add reference counting in nrf_qspi_nor_xip_enable() so that XIP is kept enabled as long as there is at least one user that needs it (boot time enabling done with CONFIG_NORDIC_QSPI_NOR_XIP also counts). Signed-off-by: Andrzej Głąbek <[email protected]> (cherry picked from commit 2d9ede3)
…ER is set to NONE When the quad-enable-requirements property is set to "NONE" or is not present, no Quad Enable operation should be performed. This fixes an issue with the mx25uw6345g flash chip that is present on the nRF54h20 DK and supports the Single I/O mode, but cannot be used in that mode. Signed-off-by: Andrzej Głąbek <[email protected]> (cherry picked from commit 8415f7f)
- replace %d with %u in two error log message format strings - add checks for maximum supported address length - correct *_WAIT_CYCLES_MAX macros used in XIP handling routines (although their values are valid, they belong to different SSI registers) - remove one unnecessary use of SPI_CTRLR0_WAIT_CYCLES_MASK - remove doubled definitions of the XIP_CTRL register bit fields Signed-off-by: Andrzej Głąbek <[email protected]> (cherry picked from commit 8b67b36)
…pecific resume After the START task is triggered, the clock that drives the SSI core needs some time to become ready. Before that, writes to SSI registers may be unsuccessful. Add a loop that performs test writes to one of the registers after the EXMIF peripheral is resumed to ensure that it is fully operable. Signed-off-by: Andrzej Głąbek <[email protected]> (cherry picked from commit 6ddb616)
- use separate code paths for TX and RX in ISR - make sending of dummy bytes in the single line mode (Standard SPI) more consistent so it can be easily extended - use value 0 instead of 0xAA for dummy bytes as there is normally no point in making noise one the MOSI line when only receiving data (it can only be useful in debugging transfers) - move all writing of data in the TX FIFO to ISR to avoid broken transfers in the single line mode (where the clock stretching is not available) when the driver is preempted right before it enables interrupts - use the TX FIFO start level also for transfers without data, so that it's not possible that the TX FIFO gets emptied between the writes of command and address fields in the single line mode - add a few comments to explain better how transfers are handled Signed-off-by: Andrzej Głąbek <[email protected]> (cherry picked from commit e4dc744)
Immediately finish an RX transfer when the RX FIFO overflow is encountered and return the -EIO error code, which better indicates the problem than -ETIMEDOUT that was returned previously in such case. Signed-off-by: Andrzej Głąbek <[email protected]> (cherry picked from commit 28dafe3)
…ingle line mode Support for 8 dummy cycles in a single line RX transaction is required for the standard JEDEC Read SFDP command. The SSI controller does not support dummy cycles in Standard SPI mode, but the driver can simulate those by just sending a dummy data byte. Signed-off-by: Andrzej Głąbek <[email protected]> (cherry picked from commit e787296)
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bjarki-andreasen
approved these changes
Jun 27, 2025
rlubos
approved these changes
Jun 30, 2025
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