Nrfx 7936 nrfx 7936 enable samples and tests on nrf54lm20a pt3

boards/native/nrf_bsim/Kconfig

@@ -45,6 +45,16 @@ config BOARD_NRF54L15BSIM_NRF54L15_CPUAPP
 	  Will produce a console Linux process which can be executed natively.
 	  It needs the BabbleSim simulator both in compile time and to execute
 
+config BOARD_NRF54LM20BSIM_NRF54LM20A_CPUAPP
+	bool
+	select SOC_SERIES_BSIM_NRF54LX
+	select SOC_COMPATIBLE_NRF54LM20A
+	select SOC_COMPATIBLE_NRF54LM20A_CPUAPP
+	select CLOCK_CONTROL
+	help
+	  Simulated NRF54LM20 Application core
+	  Will produce a console Linux process which can be executed natively.
+	  It needs the BabbleSim simulator both in compile time and to execute
 
 if SOC_SERIES_BSIM_NRFXX
 

boards/native/nrf_bsim/Kconfig.nrf54lm20bsim

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NRF54LM20BSIM
+	select SOC_POSIX

boards/native/nrf_bsim/board.yml

@@ -14,5 +14,10 @@ boards:
   vendor: zephyr
   socs:
   - name: nrf54l15
+- name: nrf54lm20bsim
+  full_name: nRF54LM20 simulated boards (BabbleSim)
+  vendor: zephyr
+  socs:
+  - name: nrf54lm20a
 # Note the 53 and 54 are referring to the real SOC yamls, but we only use their name and cpu-cluster
 # definitions. In practice these board uses the same native SOC (SOC_POSIX) as the nrf52_bsim

boards/native/nrf_bsim/board_soc.h

@@ -38,7 +38,7 @@
 #define OFFLOAD_SW_IRQ EGU0_IRQn
 #elif defined(CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUNET)
 #define OFFLOAD_SW_IRQ SWI0_IRQn
-#elif defined(CONFIG_BOARD_NRF54L15BSIM)
+#elif defined(CONFIG_SOC_SERIES_BSIM_NRF54LX)
 #define OFFLOAD_SW_IRQ SWI00_IRQn
 #endif
 

boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp.dts

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+#include <arm/nordic/nrf54lm20a_enga_cpuapp.dtsi>
+#include <../boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a-pinctrl.dtsi>
+
+/ {
+	model = "Nordic NRF54LM20 BSIM NRF54LM20A Application MCU";
+	compatible = "bsim,nrf54lm20-bsim-nrf54lm20a-cpuapp", "bsim,nrf54";
+
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,entropy = &rng;
+		zephyr,bt-c2h-uart = &uart20;
+		zephyr,flash-controller = &rram_controller;
+		zephyr,flash = &cpuapp_rram;
+	};
+
+	/delete-node/ cpus;
+	/delete-node/ sw-pwm;
+
+	soc {
+		/delete-node/ memory@20000000;
+		/delete-node/ memory@20067c00;
+
+		peripheral@50000000 {
+			/delete-node/ vpr@4c000;
+			/delete-node/ interrupt-controller@f0000000;
+			/delete-node/spi@4d000;
+			/delete-node/usbhs@5a000;
+			/delete-node/i2c@c6000;
+			/delete-node/spi@c6000;
+			/delete-node/i2c@c7000;
+			/delete-node/spi@c7000;
+			/delete-node/i2c@c8000;
+			/delete-node/spi@c8000;
+			/delete-node/pdm@d0000;
+			/delete-node/pdm@d1000;
+			/delete-node/pwm@d2000;
+			/delete-node/pwm@d3000;
+			/delete-node/pwm@d4000;
+			/delete-node/adc@d5000;
+			/delete-node/nfct@d6000;
+			/delete-node/qdec@e0000;
+			/delete-node/qdec@e1000;
+			/delete-node/tdm@e8000;
+			/delete-node/i2c@ed000;
+			/delete-node/spi@ed000;
+			/delete-node/i2c@ee000;
+			/delete-node/spi@ee000;
+			/delete-node/i2c@104000;
+			/delete-node/spi@104000;
+			/delete-node/comparator@106000;
+			/delete-node/watchdog@108000;
+			/delete-node/watchdog@109000;
+			/delete-node/regulator@120000;
+		};
+	};
+
+	rng: rng {
+		status = "okay";
+		compatible = "nordic,nrf-cracen-ctrdrbg";
+	};
+
+	psa_rng: psa-rng {
+		status = "disabled";
+	};
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		storage_partition: partition@0 {
+			label = "storage";
+			reg = <0x0 DT_SIZE_K(500)>;
+		};
+	};
+};
+
+&uart20 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart20_default>;
+	pinctrl-1 = <&uart20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart30 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+	/* These features are not yet supported by the RADIO model */
+	/delete-property/ dfe-supported;
+	/delete-property/ cs-supported;
+};
+
+&clock {
+	status = "okay";
+};

boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp.yaml

@@ -0,0 +1,17 @@
+identifier: nrf54lm20bsim/nrf54lm20a/cpuapp
+name: NRF54LM20 BabbleSim - Application Core target
+type: native
+arch: posix
+simulation:
+  - name: native
+env:
+  - BSIM_OUT_PATH
+toolchain:
+  - zephyr
+supported:
+  - counter
+  - gpio
+testing:
+  ignore_tags:
+    - modem
+    - bsim_skip_CI

boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp_defconfig

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2023 Nordic Semiconductor ASA
+
+CONFIG_CONSOLE=y
+CONFIG_NO_OPTIMIZATIONS=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y

drivers/serial/Kconfig.nrfx

@@ -60,7 +60,7 @@ config UART_NRFX_UARTE_ENHANCED_RX
 	bool "Enhanced RX handling"
 	depends on UART_ASYNC_API
 	depends on UART_NRFX_UARTE_LEGACY_SHIM
-	default y
+	default y if !(UART_0_NRF_HW_ASYNC || UART_1_NRF_HW_ASYNC || UART_2_NRF_HW_ASYNC)
 	help
 	  Enable RX handling mode which is switching buffers on timeout. This is an
 	  enhancement compared to other two modes (default and hardware assisted).

drivers/serial/Kconfig.nrfx_uart_instance

@@ -49,23 +49,18 @@ config UART_$(nrfx_uart_num)_NRF_TX_BUFFER_SIZE
 	  particular SoC.
 
 config UART_$(nrfx_uart_num)_NRF_HW_ASYNC
-	bool "[DEPRECATED] Use hardware RX byte counting"
+	bool "Use hardware RX byte counting"
 	depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
 	depends on UART_ASYNC_API
 	depends on UART_NRFX_UARTE_LEGACY_SHIM
-	depends on !UART_NRFX_UARTE_ENHANCED_RX
 	depends on HAS_HW_NRF_PPI || HAS_HW_NRF_DPPIC
 	select NRFX_GPPI
-	select DEPRECATED
 	help
 	  If default driver uses interrupts to count incoming bytes, it is possible
 	  that with higher speeds and/or high cpu load some data can be lost.
 	  It is recommended to use hardware byte counting in such scenarios.
 	  Hardware RX byte counting requires timer instance and one PPI channel.
 
-	  This options is deprecated. Use UART_NRFX_UARTE_ENHANCED_RX which supports
-	  reliable byte counting without additional HW resources (TIMER and (D)PPI).
-
 config UART_$(nrfx_uart_num)_NRF_ASYNC_LOW_POWER
 	bool "Low power mode"
 	depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)

drivers/serial/uart_nrfx_uarte.c

@@ -1611,11 +1611,11 @@ static void endrx_isr(const struct device *dev)
 		}
 
 		irq_unlock(key);
-		if (IS_ENABLED(UARTE_HAS_FRAME_TIMEOUT)) {
-			if (start_timeout && !K_TIMEOUT_EQ(async_rx->timeout, K_NO_WAIT)) {
-				k_timer_start(&async_rx->timer, async_rx->timeout, K_NO_WAIT);
-			}
+#ifdef UARTE_HAS_FRAME_TIMEOUT
+		if (start_timeout && !K_TIMEOUT_EQ(async_rx->timeout, K_NO_WAIT)) {
+			k_timer_start(&async_rx->timer, async_rx->timeout, K_NO_WAIT);
 		}
+#endif
 	}
 
 #if !defined(CONFIG_UART_NRFX_UARTE_ENHANCED_RX)
@@ -2490,6 +2490,11 @@ static int uarte_instance_init(const struct device *dev,
 		((struct pinctrl_dev_config *)cfg->pcfg)->reg = (uintptr_t)cfg->uarte_regs;
 	}
 
+	/* Apply sleep state by default.
+	 * If PM is disabled, the default state will be applied in pm_device_driver_init.
+	 */
+	(void)pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP);
+
 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
 	err = uarte_nrfx_configure(dev, &((struct uarte_nrfx_data *)dev->data)->uart_config);
 	if (err) {

modules/hal_nordic/nrfx/CMakeLists.txt

@@ -66,6 +66,8 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUFLPR NRF_FLPR)
 zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA     NRF54LM20A_ENGA_XXAA)
 zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP NRF_APPLICATION)
 zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUFLPR NRF_FLPR)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54LM20A NRF54LM20A_ENGA_XXAA)
+zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54LM20A_CPUAPP NRF_APPLICATION)
 zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120             NRF9120_XXAA)
 zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9160             NRF9160_XXAA)
 

samples/net/cellular_modem/boards/nrf9160dk_nrf52840.conf

@@ -1,6 +1,9 @@
 CONFIG_UART_ASYNC_API=y
 CONFIG_UART_1_ASYNC=y
 CONFIG_UART_1_INTERRUPT_DRIVEN=n
+# Enable HW RX byte counting. This especially matters at higher baud rates.
+CONFIG_UART_1_NRF_HW_ASYNC=y
+CONFIG_UART_1_NRF_HW_ASYNC_TIMER=1
 
 # Align with the Serial LTE Modem (SLM) application.
 CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=6000

samples/net/cellular_modem/boards/nrf9160dk_nrf9160_ns.conf

@@ -1,6 +1,9 @@
 CONFIG_UART_ASYNC_API=y
 CONFIG_UART_1_ASYNC=y
 CONFIG_UART_1_INTERRUPT_DRIVEN=n
+# Enable HW RX byte counting. This especially matters at higher baud rates.
+CONFIG_UART_1_NRF_HW_ASYNC=y
+CONFIG_UART_1_NRF_HW_ASYNC_TIMER=1
 
 # Align with the Serial LTE Modem (SLM) application.
 CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=6000

soc/Kconfig

@@ -49,6 +49,12 @@ config SOC_COMPATIBLE_NRF54L15
 config SOC_COMPATIBLE_NRF54L15_CPUAPP
 	bool
 
+config SOC_COMPATIBLE_NRF54LM20A
+	bool
+
+config SOC_COMPATIBLE_NRF54LM20A_CPUAPP
+	bool
+
 config SOC_DEPRECATED_RELEASE
 	string
 	help

tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml

@@ -51,6 +51,7 @@ tests:
       - nrf5340dk/nrf5340/cpuapp
       - nrf5340dk/nrf5340/cpunet
       - nrf54l15dk/nrf54l15/cpuapp
+      - nrf54lm20dk/nrf54lm20a/cpuapp
       - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822

tests/drivers/uart/uart_async_api/boards/nrf5340bsim_nrf5340_cpuapp.conf

@@ -0,0 +1,2 @@
+CONFIG_UART_1_NRF_HW_ASYNC_TIMER=1
+CONFIG_UART_NRFX_UARTE_ENHANCED_RX=y

tests/drivers/uart/uart_async_api/boards/nrf5340dk_nrf5340_cpuapp.conf

@@ -1 +1,3 @@
+CONFIG_UART_1_NRF_HW_ASYNC=y
+CONFIG_UART_1_NRF_HW_ASYNC_TIMER=1
 CONFIG_VAR_LENGTH_BUFFER_TEST_BUADRATE_LIMIT=57600

tests/drivers/uart/uart_async_api/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "nrf54lm20dk_nrf54lm20a_cpuapp.overlay"

tests/drivers/uart/uart_async_api/boards/nrf9160dk_nrf9160.conf

@@ -1,2 +1,4 @@
 CONFIG_ARM_MPU=n
 CONFIG_VAR_LENGTH_BUFFER_TEST_BUADRATE_LIMIT=57600
+CONFIG_UART_1_NRF_HW_ASYNC=y
+CONFIG_UART_1_NRF_HW_ASYNC_TIMER=2

tests/drivers/uart/uart_errors/boards/nrf5340dk_nrf5340_cpuapp.conf

@@ -0,0 +1,2 @@
+CONFIG_UART_1_NRF_HW_ASYNC=y
+CONFIG_UART_1_NRF_HW_ASYNC_TIMER=1

tests/drivers/uart/uart_mix_fifo_poll/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf54lm20dk_nrf54lm20a_cpuapp.overlay"