Skip to content

Riscv direct isr multithreading #3107

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 2 commits into
base: main
Choose a base branch
from
+60 −3
Open

Riscv direct isr multithreading #3107

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
0e8239a
arch: riscv: added helper config to include isr wrapper
lstnl Jul 30, 2025
fa39722
[nrf fromlist] arch:riscv: Support for Direct ISRs for RISCV targets
Rafal-Nordic Apr 24, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 9 additions & 0 deletions arch/riscv/Kconfig
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -262,6 +262,15 @@ config RISCV_GENERIC_TOOLCHAIN
Allow SOCs that have custom extended riscv ISA to still
compile with generic riscv32 toolchain.

config USE_ISR_WRAPPER
bool "Use isr_wrapper to handle interrupt and/or exception/fault"
default y if GEN_SW_ISR_TABLE
default y if MULTITHREADING
help
This is helper config to be able to use exception handling
when GEN_SW_ISR_TABLE is not used but multithreading is, which
needs exception handling and thread entry/switch functions.

config GEN_ISR_TABLES
default y

Expand Down
2 changes: 1 addition & 1 deletion arch/riscv/core/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ endif()
zephyr_library_sources_ifdef(CONFIG_FPU_SHARING fpu.c fpu.S)
zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr.S)
zephyr_library_sources_ifdef(CONFIG_USE_ISR_WRAPPER isr.S)
zephyr_library_sources_ifdef(CONFIG_RISCV_PMP pmp.c pmp.S)
zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
Expand Down
18 changes: 18 additions & 0 deletions arch/riscv/core/irq_manage.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
#include <zephyr/arch/riscv/csr.h>
#include <zephyr/irq_multilevel.h>
#include <zephyr/sw_isr_table.h>
#include <zephyr/pm/pm.h>

#ifdef CONFIG_RISCV_HAS_PLIC
#include <zephyr/drivers/interrupt_controller/riscv_plic.h>
Expand Down Expand Up @@ -75,3 +76,20 @@ int arch_irq_disconnect_dynamic(unsigned int irq, unsigned int priority,
}
#endif /* CONFIG_SHARED_INTERRUPTS */
#endif /* CONFIG_DYNAMIC_INTERRUPTS */

#ifdef CONFIG_PM
void _arch_isr_direct_pm(void)
{
unsigned int key;

/* irq_lock() does what we want for this CPU */
key = irq_lock();

if (_kernel.idle) {
_kernel.idle = 0;
pm_system_resume();
}

irq_unlock(key);
}
#endif
9 changes: 9 additions & 0 deletions arch/riscv/core/isr.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,7 @@ GTEXT(__soc_is_irq)
#endif
GTEXT(__soc_handle_irq)
GTEXT(z_riscv_fault)
GTEXT(z_irq_spurious)
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
Expand Down Expand Up @@ -331,6 +332,7 @@ no_fp: /* increment _current->arch.exception_depth */
* function (that needs to be implemented by each SOC). The result is
* returned via register a0 (1: interrupt, 0 exception)
*/

#ifdef CONFIG_RISCV_SOC_EXCEPTION_FROM_IRQ
jal ra, __soc_is_irq
bnez a0, is_interrupt
Expand Down Expand Up @@ -646,6 +648,7 @@ on_irq_stack:
*/
jal ra, __soc_handle_irq

#if defined CONFIG_GEN_SW_ISR_TABLE
/*
* Call corresponding registered function in _sw_isr_table.
* (table is 2-word wide, we should shift index accordingly)
Expand All @@ -659,6 +662,12 @@ on_irq_stack:

/* Load ISR function address in register t1 */
lr t1, RV_REGSIZE(t0)
#else
/* Load spurious interrupt function in case _sw_isr_table does not exist */
la t1, z_irq_spurious
/* NULL as parameter */
li a0, 0
#endif

/* Call ISR function */
jalr ra, t1, 0
Expand Down
14 changes: 14 additions & 0 deletions drivers/timer/nrf_grtc_timer.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -455,12 +455,26 @@
return (uint32_t)(counter_sub(counter(), last_count) / CYC_PER_TICK);
}

#if !defined(CONFIG_GEN_SW_ISR_TABLE)
ISR_DIRECT_DECLARE(nrfx_grtc_direct_irq_handler)
{
nrfx_grtc_irq_handler();
ISR_DIRECT_PM();
return 1;
}
#endif

static int sys_clock_driver_init(void)
{
nrfx_err_t err_code;

#if defined(CONFIG_GEN_SW_ISR_TABLE)
IRQ_CONNECT(DT_IRQN(GRTC_NODE), DT_IRQ(GRTC_NODE, priority), nrfx_isr,
nrfx_grtc_irq_handler, 0);
#else
IRQ_DIRECT_CONNECT(DT_IRQN(GRTC_NODE), DT_IRQ(GRTC_NODE, priority), nrfx_grtc_direct_irq_handler, 0);

Check warning on line 475 in drivers/timer/nrf_grtc_timer.c

View workflow job for this annotation

GitHub Actions / Run compliance checks on patch series (PR)

LONG_LINE 

drivers/timer/nrf_grtc_timer.c:475  line length of 109 exceeds 100 columns
irq_enable(DT_IRQN(GRTC_NODE));

Check notice on line 476 in drivers/timer/nrf_grtc_timer.c

View workflow job for this annotation

GitHub Actions / Run compliance checks on patch series (PR)

You may want to run clang-format on this change 

drivers/timer/nrf_grtc_timer.c:476 
-	IRQ_DIRECT_CONNECT(DT_IRQN(GRTC_NODE), DT_IRQ(GRTC_NODE, priority), nrfx_grtc_direct_irq_handler, 0);
+	IRQ_DIRECT_CONNECT(DT_IRQN(GRTC_NODE), DT_IRQ(GRTC_NODE, priority),
+			   nrfx_grtc_direct_irq_handler, 0);
#endif

#if defined(CONFIG_NRF_GRTC_TIMER_CLOCK_MANAGEMENT) && NRF_GRTC_HAS_CLKSEL
#if defined(CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC)
Expand Down
7 changes: 7 additions & 0 deletions include/zephyr/arch/riscv/irq.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,13 @@
z_riscv_irq_vector_set(irq_p); \
}

#ifdef CONFIG_PM
extern void _arch_isr_direct_pm(void);
#define ARCH_ISR_DIRECT_PM() _arch_isr_direct_pm()
#else
#define ARCH_ISR_DIRECT_PM() do { } while (false)
#endif

Check notice on line 91 in include/zephyr/arch/riscv/irq.h

View workflow job for this annotation

GitHub Actions / Run compliance checks on patch series (PR)

You may want to run clang-format on this change 

include/zephyr/arch/riscv/irq.h:91 
-#define ARCH_ISR_DIRECT_PM() do { } while (false)
+#define ARCH_ISR_DIRECT_PM()                                                                       \
+	do {                                                                                       \
+	} while (false)

#define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header()
#define ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap)

Expand Down
4 changes: 2 additions & 2 deletions soc/common/riscv-privileged/vector.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ GTEXT(__start)

/* imports */
GTEXT(__initialize)
#if defined(CONFIG_GEN_SW_ISR_TABLE)
#if defined(CONFIG_USE_ISR_WRAPPER)
GTEXT(_isr_wrapper)
#endif

Expand Down Expand Up @@ -41,7 +41,7 @@ SECTION_FUNC(vectors, __start)
* mtvec.base must be aligned to 64 bytes (this is done using
* CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT)
*/
#if defined(CONFIG_GEN_SW_ISR_TABLE)
#if defined(CONFIG_USE_ISR_WRAPPER)
la t0, _isr_wrapper
#else
add t0, zero, zero
Expand Down
Loading