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unclean cherry pick of power domain refactor and swext support #3175
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bjarki-andreasen
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bjarki-andreasen:ncs-v3.1-pd-refactor
Aug 11, 2025
Merged
unclean cherry pick of power domain refactor and swext support #3175
bjarki-andreasen
merged 9 commits into
nrfconnect:ncs-v3.1-branch
from
bjarki-andreasen:ncs-v3.1-pd-refactor
Aug 11, 2025
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`DT_SAME_NODE()` is judged by `==` and cannot be used as a condition for `COND_CODE_1()`. Using `IS_EQ()` to make it possible for compile-time calculation. Signed-off-by: TOKITA Hiroshi <[email protected]> (cherry picked from commit ba48d83)
Introduce the NRFS GDPWR (Global Domain Power Request) device driver and devicetree binding. Signed-off-by: Bjarki Arge Andreasen <[email protected]> (cherry picked from commit 0ec81c5)
Introduce the NRF GPIO Pad Group device driver and binding. The pad group device represents the GPIO pads (pins), contrary to a GPIO controller, which is one of the many devices which can be muxed to pads in the pad group. The pad group belong to a power domain, which is not neccesarily the same power domain as devices being muxed to the pads, like GPIO or UART. If no ACTIVE device is using any of the pads in the pad group, the pad groups power domain may be SUSPENDED. Before the pad groups power domain is SUSPENDED, pad config retention must be enabled to prevent the pads from loosing their state. That's what this device driver manages. Once retained, the pad configs and outputs are locked, even when their power domain is SUSPENDED. Signed-off-by: Bjarki Arge Andreasen <[email protected]> (cherry picked from commit 3a8651a)
…ctrl and pds Transition nrf54h away from the soc specific gpd (global power domain) driver which mixed power domains, pinctrl and gpio pin retention into a non scalable solution, forcing soc specific logic to bleed into nrf drivers. The new solution uses zephyrs PM_DEVICE based power domains to properly model the hardware layout of device and pin power domains, and moves pin retention logic out of drivers into pinctrl and gpio, which are the components which manage pins (pads). Signed-off-by: Bjarki Arge Andreasen <[email protected]> (cherry picked from commit 2b0d1ae)
…n) driver Remove the deprecated GPD (Global Power Domain) driver. Signed-off-by: Bjarki Arge Andreasen <[email protected]> (cherry picked from commit 2854115)
…e clock ctrl Update handling of fast instances to take into account whether CONFIG_CLOCK_CONTROL is enabled or not. Signed-off-by: Bjarki Arge Andreasen <[email protected]> (cherry picked from commit c326bf6)
Introduce nordic NRFS SWEXT power domain bindings and add it to relevant SoC devicetree files. Upstream PR #: 93880 Signed-off-by: Bjarki Arge Andreasen <[email protected]>
Introduce nrfx_swext device driver for NRFS SWEXT power domain device. Upstream PR #: 93880 Signed-off-by: Bjarki Arge Andreasen <[email protected]>
The nrfs_gdpwr driver has a two stage init, which requires tracking an "expected" state of the power domain, to be applied once the ipc service needed to control the power domain is ready. This was tracked with the "off" member of struct domain_data. So, "off" was initialized to false, but, should actually be initialized to true, since by default, if nothing needs the power domain, it should be turned off when ipc service is ready. To fix this, rename "off" member to "on" and adjust logic. Additionally, define the correct struct domain_data in the DOMAIN_DEFINE() macro. Can save 2 bytes. This did not cause any issue since we typecast it anyway, and its size is large enough. Upstream PR #: 94214 Signed-off-by: Bjarki Arge Andreasen <[email protected]>
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nordicjm
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unclean cherry pick of power domain refactor and swext support