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boards: Fix nRF54L10 size for the non secure target #3234

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Merged
merged 3 commits into from
Sep 15, 2025
Merged

boards: Fix nRF54L10 size for the non secure target #3234

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cdb85a7
[nrf fromtree] Revert "boards: nordic: nrf54l10_cpuapp_ns: Add workar…
Vge0rge Aug 5, 2025
9f893dd
[nrf fromtree] boards: nordic: Fix RRAM size for nRF54l10 NS
Vge0rge Aug 5, 2025
d3f1d09
[nrf fromtree] boards: ezurio: Fix RRAM size for nRF54l10 NS
Vge0rge Aug 5, 2025
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15 changes: 6 additions & 9 deletions boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,8 @@
/ {
/*
* Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support.
* - Lowest 96 kB SRAM allocated to Secure image (sram0_s).
* - Upper 96 kB SRAM allocated to Non-Secure image (sram0_ns).
* - Lowest 72 kB SRAM allocated to Secure image (sram0_s).
* - Upper 72 kB SRAM allocated to Non-Secure image (sram0_ns).
*
* nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for
* the FLPR MCU.
Expand All @@ -59,14 +59,11 @@
};

&cpuapp_rram {
/* TODO: revert this hack when TF-M update is available that fixes partition sizes */
reg = <0x0 DT_SIZE_K(1022)>;

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the
/* nRF54L10 has 1012 kB of non volatile memory (RRAM) but the
* last 62kB are reserved for the FLPR MCU.
*
* This static layout needs to be the same with the upstream TF-M layout in the
Expand Down Expand Up @@ -95,12 +92,12 @@

slot0_ns_partition: partition@6A000 {
label = "image-0-nonsecure";
reg = <0x0006A000 DT_SIZE_K(504)>;
reg = <0x0006A000 DT_SIZE_K(494)>;
};

storage_partition: partition@E8000 {
storage_partition: partition@E5800 {
label = "storage";
reg = <0x000E8000 DT_SIZE_K(32)>;
reg = <0x000E5800 DT_SIZE_K(32)>;
};
};
};
Expand Down
2 changes: 1 addition & 1 deletion boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ toolchain:
- zephyr
sysbuild: true
ram: 192
flash: 1022
flash: 1012
supported:
- adc
- gpio
Expand Down
15 changes: 6 additions & 9 deletions boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -31,8 +31,8 @@
/ {
/*
* Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support.
* - Lowest 96 kB SRAM allocated to Secure image (sram0_s).
* - Upper 96 kB SRAM allocated to Non-Secure image (sram0_ns).
* - Lowest 72 kB SRAM allocated to Secure image (sram0_s).
* - Upper 72 kB SRAM allocated to Non-Secure image (sram0_ns).
*
* nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for
* the FLPR MCU.
Expand All @@ -58,14 +58,11 @@
};

&cpuapp_rram {
/* TODO: revert this hack when TF-M update is available that fixes partition sizes */
reg = <0x0 DT_SIZE_K(1022)>;

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the
/* nRF54L10 has 1012 kB of non volatile memory (RRAM) but the
* last 62kB are reserved for the FLPR MCU.
*
* This static layout needs to be the same with the upstream TF-M layout in the
Expand Down Expand Up @@ -94,12 +91,12 @@

slot0_ns_partition: partition@6A000 {
label = "image-0-nonsecure";
reg = <0x0006A000 DT_SIZE_K(504)>;
reg = <0x0006A000 DT_SIZE_K(494)>;
};

storage_partition: partition@E8000 {
storage_partition: partition@E5800 {
label = "storage";
reg = <0x000E8000 DT_SIZE_K(32)>;
reg = <0x000E5800 DT_SIZE_K(32)>;
};
};
};
Expand Down
2 changes: 1 addition & 1 deletion boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ toolchain:
- gnuarmemb
- zephyr
ram: 192
flash: 1022
flash: 1012
supported:
- adc
- gpio
Expand Down