[nrf fromtree] boards: nrf9280pdk: Add revision 0.2.0

boards/nordic/nrf9280pdk/board.yml

@@ -9,3 +9,10 @@ board:
       cpucluster: cpuppr
     - name: iron
       cpucluster: cpuapp
+  revision:
+    format: major.minor.patch
+    default: 0.2.0
+    exact: false
+    revisions:
+    - name: 0.1.0
+    - name: 0.2.0

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl_0_2_0.dtsi

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	/omit-if-no-ref/ uart135_default: uart135_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 6)>,
+				<NRF_PSEL(UART_RTS, 2, 7)>;
+		};
+
+		group3 {
+			bias-pull-up;
+			psels = <NRF_PSEL(UART_RX, 2, 4)>,
+				<NRF_PSEL(UART_CTS, 2, 5)>;
+		};
+	};
+
+	/omit-if-no-ref/ uart135_sleep: uart135_sleep {
+		group1 {
+			low-power-enable;
+			psels = <NRF_PSEL(UART_TX, 2, 6)>,
+				<NRF_PSEL(UART_RX, 2, 4)>,
+				<NRF_PSEL(UART_RTS, 2, 7)>,
+				<NRF_PSEL(UART_CTS, 2, 5)>;
+		};
+	};
+
+	/omit-if-no-ref/ uart136_default: uart136_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 9)>;
+		};
+
+		group3 {
+			bias-pull-up;
+			psels = <NRF_PSEL(UART_RX, 1, 10)>,
+				<NRF_PSEL(UART_CTS, 1, 7)>;
+		};
+	};
+
+	/omit-if-no-ref/ uart136_sleep: uart136_sleep {
+		group1 {
+			low-power-enable;
+			psels = <NRF_PSEL(UART_TX, 1, 11)>,
+				<NRF_PSEL(UART_RX, 1, 10)>,
+				<NRF_PSEL(UART_RTS, 1, 9)>,
+				<NRF_PSEL(UART_CTS, 1, 7)>;
+		};
+	};
+};

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts

@@ -24,7 +24,6 @@
 		zephyr,flash = &mram1x;
 		zephyr,sram = &cpuapp_data;
 		zephyr,shell-uart = &uart136;
-		zephyr,ieee802154 = &cpuapp_ieee802154;
 		zephyr,bt-hci = &bt_hci_ipc0;
 		nordic,802154-spinel-ipc = &ipc0;
 		zephyr,entropy = &prng;
@@ -291,10 +290,6 @@ ipc0: &cpuapp_cpurad_ipc {
 	};
 };
 
-&cpuapp_ieee802154 {
-	status = "okay";
-};
-
 zephyr_udc0: &usbhs {
 	status = "okay";
 };

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp_0_2_0.overlay

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf9280pdk_nrf9280-pinctrl_0_2_0.dtsi"
+
+/ {
+	aliases {
+		pwm-led0 = &pwm_led2; /* Alias for compatibility with samples that use pwm-led0 */
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 0";
+		};
+
+		led1: led_1 {
+			gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 1";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 2";
+		};
+
+		led3: led_3 {
+			gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 3";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		/delete-node/ pwm_led_0;
+
+		/*
+		 * There is no valid hardware configuration to pass PWM signal on pins 0 and 1.
+		 * First valid config is P9.2. This corresponds to LED 2.
+		 * Signal on PWM130's channel 0 can be passed directly on GPIO Port 9 pin 2.
+		 */
+		pwm_led2: pwm_led_2 {
+			pwms = <&pwm130 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+};

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_0_2_0.overlay

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf9280pdk_nrf9280-pinctrl_0_2_0.dtsi"

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_0_2_0.overlay

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf9280pdk_nrf9280-pinctrl_0_2_0.dtsi"