[nrf fromtree] Cherry-pick recent changes in the mspi_dw driver #3261
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… generic case Supply empty vendor specific macros for cases where vendor specific functions are not needed by driver. Signed-off-by: Daniel DeGrasse <[email protected]> (cherry picked from commit 98c0cc4)
The remainder of this driver functions when pin control is disabled, so make the include conditional as well to fully support this case. Signed-off-by: Daniel DeGrasse <[email protected]> (cherry picked from commit cb31e67)
…nterrupts Multilevel interrupts require that the irq number be read with DT_IRQN, so update the driver to use this macro. Signed-off-by: Daniel DeGrasse <[email protected]> (cherry picked from commit 5dbaa86)
Bitmask offsets for the MSPI_DW peripheral are incorrect for the 4.03a databook for the DW APB SSI. Add a "v2" compatible to handle these changed offsets. The compatible does not define new binding properties, just modifies the register offsets. Additionally, handle writing the DFS32 mask for v2 of this compatible, as newer IP supports a dataframe size up to 32 bits. Signed-off-by: Daniel DeGrasse <[email protected]> (cherry picked from commit 59d8fbc)
…ming The SSI DW peripheral supports an RX_SAMPLE_DLY register in some instances- this register controls the number of clock cycles from the default sample time before the RX input is actually sampled. This can be used to improve reliability when operating the SSI at a higher clock speed. Add an implementation of the mspi_timing_cfg api, and header to define the identifier so that users can configure this parameter Signed-off-by: Daniel DeGrasse <[email protected]> (cherry picked from commit 9c829a1)
The designware controller has an *interesting* implementation of the CS signal- CS will be de-asserted whenever the TX FIFO is empty, so slower cores may see CS de-assert prematurely if they cannot keep pace with their SPI peripheral. To help reduce odds of de-assertion, implement the following changes: - don't write SER bit until directly before we enable interrupts, so that transfers don't start early - prefix the TX FIFO before writing SER, so the FIFO can drain a bit before have to service an interrupt Signed-off-by: Daniel DeGrasse <[email protected]> (cherry picked from commit e425b3d)
Support DDR mode within the mspi_dw driver Signed-off-by: Daniel DeGrasse <[email protected]> (cherry picked from commit fc64fec)
…ed at entry Some systems (IE cores with bootloaders) may not disable the DW SPI peripheral at boot time. Make sure the peripheral is disabled before we try to configure it. Signed-off-by: Daniel DeGrasse <[email protected]> (cherry picked from commit a294653)
…RIVE_EDGE setting TXD_DRIVE_EDGE setting will typically be set to BAUDR/4 for DDR mode, but this may not cover all cases. Add a configurable multiplier and divisor to apply to the BAUDR value so the value's relation to BAUDR can be customized. Signed-off-by: Daniel DeGrasse <[email protected]> (cherry picked from commit 6e3a8da)
…PI_XIP disabled Move `api_timing_config()` impl outside of the block gated behind CONFIG_MSPI_XIP. Signed-off-by: Utsav Munendra <[email protected]> (cherry picked from commit 030b9f3)
Add possibility of using data strobe signal (DQS) called RXDS in the SSI documentation. This signal may be necessary to make use of DDR modes. Remove also a TODO comment that should have been removed when support for DDR was added in fc64fec. Signed-off-by: Andrzej Głąbek <[email protected]> (cherry picked from commit 0e1dfd9)
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rlubos
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Sep 11, 2025
nordic-piks
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Sep 11, 2025
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... that are needed to use Dual Data Rate modes.