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[nrf fromlist] arch: Allow to specify memory for S2RAM resume #3275

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Merged
merged 5 commits into from
Sep 17, 2025
Merged

[nrf fromlist] arch: Allow to specify memory for S2RAM resume #3275

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9d01d3a
Revert "[nrf noup] soc/nordic/nrf54h/pm_s2ram: S2RAM resume hardening"
tomchy Sep 16, 2025
6635e16
[nrf noup] boards: Align board DTS with upstream.
tomchy Sep 15, 2025
db3cc04
[nrf fromlist] arch: Allow to specify memory for S2RAM resume
tomchy Sep 16, 2025
8036c40
[nrf fromlist] boards: Define pm_s2ram_stack for nRF54H20
tomchy Sep 16, 2025
2dc2c8f
[nrf noup] soc/nordic/nrf54h/pm_s2ram: S2RAM resume hardening
nvlsianpu Sep 5, 2025
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12 changes: 12 additions & 0 deletions arch/arm/core/cortex_m/reset.S
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,17 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
#endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

#if defined(CONFIG_PM_S2RAM)
#if DT_NODE_EXISTS(DT_NODELABEL(pm_s2ram_stack)) &&\
DT_NODE_HAS_COMPAT(DT_NODELABEL(pm_s2ram_stack), zephyr_memory_region)
/* In certain scenarios, the interrupt stack is actually not safe to overwrite.
* For example, when MCUboot is used, the bootloader's "z_interrupt_stack" and the
* loaded image's "z_interrupt_stacks" are NOT at the same address, and writing to
* the former would corrupt unrelated data from the loaded image. To support such
* scenarios, if the Device Tree provides a specially named "zephyr,memory-region",
* use it as the stack to run arch_pm_s2ram_resume instead of the interrupt stack.
*/
ldr r0, =DT_REG_ADDR(DT_NODELABEL(pm_s2ram_stack)) + DT_REG_SIZE(DT_NODELABEL(pm_s2ram_stack))
#else
/*
* Temporarily set MSP to interrupt stack so that arch_pm_s2ram_resume can
* use stack for calling pm_s2ram_mark_check_and_clear.
Expand All @@ -95,6 +106,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
* a short while, there is no change in behavior in either of the paths.
*/
ldr r0, =z_interrupt_stacks + CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
#endif
msr msp, r0

bl arch_pm_s2ram_resume
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11 changes: 9 additions & 2 deletions boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts
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Expand Up @@ -343,12 +343,19 @@ zephyr_udc0: &usbhs {

/* Trim this RAM block for making room on all run-time common S2RAM cpu context. */
&cpuapp_ram0 {
reg = <0x22000000 (DT_SIZE_K(32) - 36)>;
ranges = <0x0 0x22000000 (0x8000 - 0x24)>;
reg = <0x22000000 (DT_SIZE_K(32) - 52)>;
ranges = <0x0 0x22000000 (0x8000 - 0x34)>;
};

/ {
soc {
/* temporary stack for S2RAM resume logic */
pm_s2ram_stack: cpuapp_s2ram_stack@22007fcc {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x22007fcc 16>;
zephyr,memory-region = "pm_s2ram_stack";
};

/* run-time common mcuboot S2RAM support section */
mcuboot_s2ram: cpuapp_s2ram@22007fdc {
compatible = "zephyr,memory-region", "mmio-sram";
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5 changes: 5 additions & 0 deletions subsys/pm/Kconfig
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Expand Up @@ -41,6 +41,11 @@ config PM_S2RAM
When enabled on Cortex-M, and a 'zephyr,memory-region' compatible node with nodelabel
'pm_s2ram' is defined in DT, _cpu_context symbol (located in arch/arm/core/cortex_m/pm_s2ram.c)
is placed in linker section given by 'zephyr,memory-region' property of aforementioned node.
Additionally on Cortex-M, if a 'zephyr,memory-region' compatible node with nodelabel
'pm_s2ram_stack' is defined in DT, this region will be used as a temporary program stack
for the S2RAM resume logic. The assembly reset handling code itself makes a single push of
the return address, but the SoC-specific function (pm_s2ram_mark_check_and_clear) must be
analyzed to determine the required stack size.

config PM_S2RAM_CUSTOM_MARKING
bool "Use custom marking functions"
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