Update collab nrfx 4.0

.github/workflows/manifest-PR.yml

@@ -1,7 +1,7 @@
 name: handle manifest PR
 on:
   pull_request_target:
-    types: [opened, synchronize, closed]
+    types: [opened, synchronize, closed, reopened]
     branches:
       - main
 

.gitignore

@@ -102,6 +102,7 @@ MaintainersFormat.txt
 ModulesMaintainers.txt
 Nits.txt
 Pylint.txt
+PythonCompat.txt
 Ruff.txt
 SphinxLint.txt
 SysbuildKconfig.txt

Kconfig.zephyr

@@ -7,7 +7,7 @@
 
 source "Kconfig.constants"
 
-osource "${APPLICATION_SOURCE_DIR}/VERSION"
+osource "$(APPLICATION_SOURCE_DIR)/VERSION"
 
 # Include Kconfig.defconfig files first so that they can override defaults and
 # other symbol/choice properties by adding extra symbol/choice definitions.
@@ -967,7 +967,7 @@ config BUILD_OUTPUT_STRIP_PATHS
 	bool "Strip absolute paths from binaries"
 	default y
 	help
-	  If the compiler supports it, strip the ${ZEPHYR_BASE} prefix from the
+	  If the compiler supports it, strip the $(ZEPHYR_BASE) prefix from the
 	  __FILE__ macro used in __ASSERT*, in the
 	  .noinit."/home/joe/zephyr/fu/bar.c" section names and in any
 	  application code.

arch/arm/core/cortex_m/reset.S

@@ -83,6 +83,17 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
 #endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */
 
 #if defined(CONFIG_PM_S2RAM)
+#if DT_NODE_EXISTS(DT_NODELABEL(pm_s2ram_stack)) &&\
+	DT_NODE_HAS_COMPAT(DT_NODELABEL(pm_s2ram_stack), zephyr_memory_region)
+    /* In certain scenarios, the interrupt stack is actually not safe to overwrite.
+     * For example, when MCUboot is used, the bootloader's "z_interrupt_stack" and the
+     * loaded image's "z_interrupt_stacks" are NOT at the same address, and writing to
+     * the former would corrupt unrelated data from the loaded image. To support such
+     * scenarios, if the Device Tree provides a specially named "zephyr,memory-region",
+     * use it as the stack to run arch_pm_s2ram_resume instead of the interrupt stack.
+     */
+    ldr r0, =DT_REG_ADDR(DT_NODELABEL(pm_s2ram_stack)) + DT_REG_SIZE(DT_NODELABEL(pm_s2ram_stack))
+#else
     /*
      * Temporarily set MSP to interrupt stack so that arch_pm_s2ram_resume can
      * use stack for calling pm_s2ram_mark_check_and_clear.
@@ -95,6 +106,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
      * a short while, there is no change in behavior in either of the paths.
      */
     ldr r0, =z_interrupt_stacks + CONFIG_ISR_STACK_SIZE + MPU_GUARD_ALIGN_AND_SIZE
+#endif
     msr msp, r0
 
     bl arch_pm_s2ram_resume

boards/arm/mps4/Kconfig.defconfig

@@ -0,0 +1,23 @@
+# Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE320_FVP
+
+if SERIAL
+
+config UART_INTERRUPT_DRIVEN
+	default y
+
+endif # SERIAL
+
+if ROMSTART_RELOCATION_ROM && (BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE320_FVP)
+
+config ROMSTART_REGION_ADDRESS
+	default $(dt_nodelabel_reg_addr_hex,itcm)
+
+config ROMSTART_REGION_SIZE
+	default $(dt_nodelabel_reg_size_hex,itcm,0,k)
+
+endif
+
+endif

boards/arm/mps4/Kconfig.mps4

@@ -0,0 +1,7 @@
+# Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MPS4
+	select SOC_SERIES_MPS4
+	select SOC_MPS4_CORSTONE315 if BOARD_MPS4_CORSTONE315_FVP || BOARD_MPS4_CORSTONE315_FVP_NS
+	select SOC_MPS4_CORSTONE320 if BOARD_MPS4_CORSTONE320_FVP || BOARD_MPS4_CORSTONE320_FVP_NS

boards/arm/mps4/board.cmake

@@ -0,0 +1,49 @@
+# Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+#
+# Default emulation:
+#     FVP  is used by default for corstone320/fvp.
+#
+
+
+if(CONFIG_BOARD_MPS4_CORSTONE315_FVP OR CONFIG_BOARD_MPS4_CORSTONE315_FVP_NS)
+  set(SUPPORTED_EMU_PLATFORMS armfvp)
+  set(ARMFVP_BIN_NAME FVP_Corstone_SSE-315)
+elseif(CONFIG_BOARD_MPS4_CORSTONE320_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP_NS)
+  set(SUPPORTED_EMU_PLATFORMS armfvp)
+  set(ARMFVP_BIN_NAME FVP_Corstone_SSE-320)
+endif()
+
+if(CONFIG_BOARD_MPS4_CORSTONE315_FVP OR CONFIG_BOARD_MPS4_CORSTONE320_FVP)
+    set(ARMFVP_FLAGS
+      # default is '0x11000000' but should match cpu<i>.INITSVTOR which is 0.
+      -C mps4_board.subsystem.iotss3_systemcontrol.INITSVTOR_RST=0
+      # default is 0x8, this change is needed since we split flash into itcm
+      # and sram and it reduces the number of available mpu regions causing a
+      # few MPU tests to fail.
+      -C mps4_board.subsystem.cpu0.MPU_S=16
+    )
+endif()
+
+if(CONFIG_BUILD_WITH_TFM)
+  set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex)
+endif()
+
+# FVP Parameters
+# -C indicate a config option in the form of:
+#   instance.parameter=value
+# Run the FVP with --list-params to list all options
+set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
+  -C mps4_board.uart0.out_file=-
+  -C mps4_board.uart0.unbuffered_output=1
+  -C mps4_board.uart1.out_file=-
+  -C mps4_board.uart1.unbuffered_output=1
+  -C mps4_board.uart2.out_file=-
+  -C mps4_board.uart2.unbuffered_output=1
+  -C mps4_board.visualisation.disable-visualisation=1
+  -C mps4_board.telnetterminal0.start_telnet=0
+  -C mps4_board.telnetterminal1.start_telnet=0
+  -C mps4_board.telnetterminal2.start_telnet=0
+  -C vis_hdlcd.disable_visualisation=1
+  )

boards/arm/mps4/board.yml

@@ -0,0 +1,15 @@
+board:
+  name: mps4
+  full_name: MPS4
+  vendor: arm
+  socs:
+  - name: 'corstone315'
+    variants:
+    - name: 'fvp'
+      variants:
+      - name: 'ns'
+  - name: 'corstone320'
+    variants:
+    - name: 'fvp'
+      variants:
+      - name: 'ns'

boards/arm/mps4/mps4-pinctrl.dtsi

@@ -0,0 +1,68 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/arm-mps4-pinctrl.h>
+
+&pinctrl {
+	/omit-if-no-ref/  uart3_default: uart3_default {
+		group1 {
+			pinmux = <UART3_TXD_EXP>;
+		};
+
+		group2 {
+			pinmux = <UART3_RXD_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ uart4_default: uart4_default {
+		group1 {
+			pinmux = <UART4_TXD_EXP>;
+		};
+
+		group2 {
+			pinmux = <UART4_RXD_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi3_default: spi3_default {
+		group1 {
+			pinmux = <SPI3_SS_EXP>, <SPI3_MOSI_EXP>,
+				 <SPI3_SCK_EXP>;
+		};
+
+		group2 {
+			pinmux = <SPI3_MISO_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi4_default: spi4_default {
+		group1 {
+			pinmux = <SPI4_SS_EXP>, <SPI4_MOSI_EXP>, <SPI4_SCK_EXP>;
+		};
+
+		group2 {
+			pinmux = <SPI4_MISO_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ sbcon2_default: sbcon2_default {
+		group1 {
+			pinmux = <SBCON2_SDA_EXP>, <SBCON2_SCL_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ sbcon3_default: sbcon3_default {
+		group1 {
+			pinmux = <SBCON3_SDA_EXP>, <SBCON3_SCL_EXP>;
+			input-enable;
+		};
+	};
+};

boards/arm/mps4/mps4_common.dtsi

@@ -0,0 +1,121 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* /dts-v1/; */
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <mem.h>
+
+/ {
+	aliases {
+		led0 = &led_0;
+		led1 = &led_1;
+		sw0 = &user_button_0;
+		sw1 = &user_button_1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_0: led_0 {
+			gpios = <&gpio_led0 0>;
+			label = "USERLED0";
+		};
+
+		led_1: led_1 {
+			gpios = <&gpio_led0 1>;
+			label = "USERLED1";
+		};
+
+		led_2: led_2 {
+			gpios = <&gpio_led0 2>;
+			label = "USERLED2";
+		};
+
+		led_3: led_3 {
+			gpios = <&gpio_led0 3>;
+			label = "USERLED3";
+		};
+
+		led_4: led_4 {
+			gpios = <&gpio_led0 4>;
+			label = "USERLED4";
+		};
+
+		led_5: led_5 {
+			gpios = <&gpio_led0 5>;
+			label = "USERLED5";
+		};
+
+		led_6: led_6 {
+			gpios = <&gpio_led0 6>;
+			label = "USERLED6";
+		};
+
+		led_7: led_7 {
+			gpios = <&gpio_led0 7>;
+			label = "USERLED7";
+		};
+
+		led_8: led_8 {
+			gpios = <&gpio_led0 8>;
+			label = "PB1LED";
+		};
+
+		led_9: led_9 {
+			gpios = <&gpio_led0 9>;
+			label = "PB2LED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button_0: button_0 {
+			label = "USERPB0";
+			gpios = <&gpio_button 0>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		user_button_1: button_1 {
+			label = "USERPB1";
+			gpios = <&gpio_button 1>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	null_ptr_detect: null_ptr_detect@0 {
+		compatible = "zephyr,memory-region";
+		/* 0 - CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE> */
+		reg = <0x0 0x400>;
+		zephyr,memory-region = "NULL_PTR_DETECT";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) )>;
+	};
+
+	/* DDR4 - 2G, alternates non-secure/secure every 256M */
+	ddr4: memory@60000000 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)
+		       0x70000000 DT_SIZE_M(256)
+		       0x80000000 DT_SIZE_M(256)
+		       0x90000000 DT_SIZE_M(256)
+		       0xa0000000 DT_SIZE_M(256)
+		       0xb0000000 DT_SIZE_M(256)
+		       0xc0000000 DT_SIZE_M(256)
+		       0xd0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
+
+#include "mps4-pinctrl.dtsi"