Idle sample fixes nrf54h

boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi

@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is common to the secure and non-secure domain */
+
+#include <nordic/nrf54l20_enga_cpuapp.dtsi>
+#include "nrf54l20pdk_nrf54l20-common.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,shell-uart = &uart20;
+		zephyr,uart-mcumgr = &uart20;
+		zephyr,bt-mon-uart = &uart20;
+		zephyr,bt-c2h-uart = &uart20;
+		zephyr,flash-controller = &rram_controller;
+		zephyr,flash = &cpuapp_rram;
+		zephyr,bt-hci = &bt_hci_sdc;
+		zephyr,ieee802154 = &ieee802154;
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&lfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15500>;
+};
+
+&hfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15000>;
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(449)>;
+		};
+
+		slot0_ns_partition: partition@80400 {
+			label = "image-0-nonsecure";
+			reg = <0x80400 DT_SIZE_K(449)>;
+		};
+
+		slot1_partition: partition@f0800 {
+			label = "image-1";
+			reg = <0xf0800 DT_SIZE_K(449)>;
+		};
+
+		slot1_ns_partition: partition@160c00 {
+			label = "image-1-nonsecure";
+			reg = <0x160c00 DT_SIZE_K(449)>;
+		};
+
+		storage_partition: partition@1d1000 {
+			label = "storage";
+			reg = <0x1d1000 DT_SIZE_K(36)>;
+		};
+	};
+};
+
+&uart20 {
+	status = "okay";
+};
+
+&nfct {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&bt_hci_sdc {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};

drivers/adc/adc_nrfx_saadc.c

@@ -12,8 +12,11 @@
 #include <zephyr/linker/devicetree_regions.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/device_runtime.h>
 #include <dmm.h>
 #include <soc.h>
+#include <hal/nrf_gpio.h>
 
 LOG_MODULE_REGISTER(adc_nrfx_saadc, CONFIG_ADC_LOG_LEVEL);
 
@@ -198,6 +201,10 @@
 
 	*pin_p = saadc_psels[channel_cfg->input_positive];
 
+#if NRF_GPIO_HAS_RETENTION_SETCLEAR
+	nrf_gpio_pin_retain_disable(saadc_psels[channel_cfg->input_positive]);
+#endif
+
 	if (channel_cfg->differential) {
 		if (channel_cfg->input_negative > ARRAY_SIZE(saadc_psels) ||
 		    (IS_ENABLED(CONFIG_NRF_PLATFORM_HALTIUM) &&
@@ -210,6 +217,11 @@
 		*pin_n = channel_cfg->input_negative == NRF_SAADC_GND ?
 			 NRF_SAADC_INPUT_DISABLED :
 			 saadc_psels[channel_cfg->input_negative];
+
+#if NRF_GPIO_HAS_RETENTION_SETCLEAR
+		nrf_gpio_pin_retain_disable(saadc_psels[channel_cfg->input_negative]);
+#endif
+
 	} else {
 		*pin_n = NRF_SAADC_INPUT_DISABLED;
 	}
@@ -725,10 +737,19 @@
 {
 	int error;
 
+	error = pm_device_runtime_get(dev);
+	if (error) {
+		return error;
+	}
+
 	adc_context_lock(&m_data.ctx, false, NULL);
 	error = start_read(dev, sequence);
 	adc_context_release(&m_data.ctx, error);
 
+	if (pm_device_runtime_put(dev)) {
+		LOG_ERR("PM put failed");
+	}
+
 	return error;
 }
 
@@ -778,6 +799,13 @@
 	}
 }
 
+static int saadc_pm_handler(const struct device *dev, enum pm_device_action action)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(action);
+	return 0;
+}
+
 static int init_saadc(const struct device *dev)
 {
 	nrfx_err_t err;
@@ -795,7 +823,7 @@
 
 	adc_context_unlock_unconditionally(&m_data.ctx);
 
-	return 0;
+	return pm_device_driver_init(dev, saadc_pm_handler);
 }
 
 static DEVICE_API(adc, adc_nrfx_driver_api) = {
@@ -838,5 +866,7 @@
 
 NRF_DT_CHECK_NODE_HAS_REQUIRED_MEMORY_REGIONS(DT_DRV_INST(0));
 
-DEVICE_DT_INST_DEFINE(0, init_saadc, NULL, NULL, NULL, POST_KERNEL,
-		      CONFIG_ADC_INIT_PRIORITY, &adc_nrfx_driver_api);
+PM_DEVICE_DT_INST_DEFINE(0, saadc_pm_handler);
+DEVICE_DT_INST_DEFINE(0, init_saadc, PM_DEVICE_DT_INST_GET(0), NULL,
+		      NULL, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,
+		      &adc_nrfx_driver_api);

drivers/can/can_nrf.c

@@ -139,6 +139,11 @@ static int configure_hsfll(const struct device *dev, bool on)
 	const struct can_nrf_config *config = mcan_config->custom;
 	struct nrf_clock_spec spec = { 0 };
 
+	if (config->hsfll == NULL) {
+		/* Frequency fixed at max */
+		return 0;
+	}
+
 	/* If CAN is on, HSFLL frequency >= AUXPLL frequency */
 	if (on) {
 		int ret;
@@ -158,7 +163,7 @@ static int can_nrf_init(const struct device *dev)
 	const struct can_nrf_config *config = mcan_config->custom;
 	int ret;
 
-	if (!device_is_ready(config->auxpll) || !device_is_ready(config->hsfll)) {
+	if (!device_is_ready(config->auxpll)) {
 		return -ENODEV;
 	}
 
@@ -215,7 +220,7 @@ static int can_nrf_init(const struct device *dev)
 		.mram = CAN_MCAN_DT_INST_MRAM_ADDR(n),                                             \
 		.auxpll = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, auxpll)),                   \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
-		.hsfll = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, hsfll)),                     \
+		.hsfll = DEVICE_DT_GET_OR_NULL(DT_INST_CLOCKS_CTLR_BY_NAME(n, hsfll)),             \
 		.irq = DT_INST_IRQN(n),                                                            \
 		.irq_configure = can_nrf_irq_configure##n,                                         \
 	};                                                                                         \