nordic: Alignment to the new GPPI API

drivers/counter/counter_nrfx_rtc.c

@@ -11,11 +11,7 @@
 #endif
 #include <haly/nrfy_rtc.h>
 #include <zephyr/sys/atomic.h>
-#ifdef DPPI_PRESENT
-#include <nrfx_dppi.h>
-#else
-#include <nrfx_ppi.h>
-#endif
+#include <helpers/nrfx_gppi.h>
 
 #define LOG_MODULE_NAME counter_rtc
 #include <zephyr/logging/log.h>
@@ -58,7 +54,7 @@ struct counter_nrfx_data {
 	/* Store channel interrupt pending and CC adjusted flags. */
 	atomic_t ipend_adj;
 #if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
-	uint8_t ppi_ch;
+	nrfx_gppi_handle_t ppi_handle;
 #endif
 };
 
@@ -379,41 +375,21 @@ static int ppi_setup(const struct device *dev, uint8_t chan)
 	struct counter_nrfx_data *data = dev->data;
 	NRF_RTC_Type *rtc = nrfx_config->rtc;
 	nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
-	nrfx_err_t result;
+	uint32_t eep = nrf_rtc_event_address_get(rtc, evt);
+	uint32_t tep = nrfy_rtc_task_address_get(rtc, NRF_RTC_TASK_CLEAR);
+	int err;
 
 	if (!nrfx_config->use_ppi) {
 		return 0;
 	}
 
 	nrfy_rtc_event_enable(rtc, NRF_RTC_CHANNEL_INT_MASK(chan));
-#ifdef DPPI_PRESENT
-	nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);
-
-	result = nrfx_dppi_channel_alloc(&dppi, &data->ppi_ch);
-	if (result != NRFX_SUCCESS) {
-		ERR("Failed to allocate PPI channel.");
-		return -ENODEV;
+	err = nrfx_gppi_conn_alloc(eep, tep, &data->ppi_handle);
+	if (err < 0) {
+		return err;
 	}
-
-	nrfy_rtc_subscribe_set(rtc, NRF_RTC_TASK_CLEAR, data->ppi_ch);
-	nrfy_rtc_publish_set(rtc, evt, data->ppi_ch);
-	(void)nrfx_dppi_channel_enable(&dppi, data->ppi_ch);
-#else /* DPPI_PRESENT */
-	uint32_t evt_addr;
-	uint32_t task_addr;
-
-	evt_addr = nrfy_rtc_event_address_get(rtc, evt);
-	task_addr = nrfy_rtc_task_address_get(rtc, NRF_RTC_TASK_CLEAR);
-
-	result = nrfx_ppi_channel_alloc(&data->ppi_ch);
-	if (result != NRFX_SUCCESS) {
-		ERR("Failed to allocate PPI channel.");
-		return -ENODEV;
-	}
-	(void)nrfx_ppi_channel_assign(data->ppi_ch, evt_addr, task_addr);
-	(void)nrfx_ppi_channel_enable(data->ppi_ch);
+	nrfx_gppi_conn_enable(data->ppi_handle);
 #endif
-#endif /* CONFIG_COUNTER_RTC_WITH_PPI_WRAP */
 	return 0;
 }
 
@@ -422,25 +398,17 @@ static void ppi_free(const struct device *dev, uint8_t chan)
 #if CONFIG_COUNTER_RTC_WITH_PPI_WRAP
 	const struct counter_nrfx_config *nrfx_config = dev->config;
 	struct counter_nrfx_data *data = dev->data;
-	uint8_t ppi_ch = data->ppi_ch;
 	NRF_RTC_Type *rtc = nrfx_config->rtc;
+	nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
+	uint32_t eep = nrf_rtc_event_address_get(rtc, evt);
+	uint32_t tep = nrfy_rtc_task_address_get(rtc, NRF_RTC_TASK_CLEAR);
 
 	if (!nrfx_config->use_ppi) {
 		return;
 	}
 	nrfy_rtc_event_disable(rtc, NRF_RTC_CHANNEL_INT_MASK(chan));
-#ifdef DPPI_PRESENT
-	nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
-	nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);
-
-	(void)nrfx_dppi_channel_disable(&dppi, ppi_ch);
-	nrfy_rtc_subscribe_clear(rtc, NRF_RTC_TASK_CLEAR);
-	nrfy_rtc_publish_clear(rtc, evt);
-	(void)nrfx_dppi_channel_free(&dppi, ppi_ch);
-#else /* DPPI_PRESENT */
-	(void)nrfx_ppi_channel_disable(ppi_ch);
-	(void)nrfx_ppi_channel_free(ppi_ch);
-#endif
+	nrfx_gppi_conn_disable(data->ppi_handle);
+	nrfx_gppi_conn_free(eep, tep, data->ppi_handle);
 #endif
 }
 

drivers/display/Kconfig.nrf_led_matrix

@@ -6,7 +6,7 @@ config DISPLAY_NRF_LED_MATRIX
 	default y
 	depends on DT_HAS_NORDIC_NRF_LED_MATRIX_ENABLED
 	select NRFX_GPIOTE
-	select NRFX_PPI if HAS_HW_NRF_PPI
+	select NRFX_GPPI
 	help
 	  Enable driver for a LED matrix with rows and columns driven by
 	  GPIOs. The driver allows setting one of 256 levels of brightness

drivers/display/display_nrf_led_matrix.c

@@ -13,9 +13,7 @@
 #include <hal/nrf_pwm.h>
 #endif
 #include <nrfx_gpiote.h>
-#ifdef PPI_PRESENT
-#include <nrfx_ppi.h>
-#endif
+#include <helpers/nrfx_gppi.h>
 #include <nrf_peripherals.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
@@ -438,21 +436,12 @@
 	nrf_pwm_shorts_set(dev_config->pwm, NRF_PWM_SHORT_SEQEND0_STOP_MASK);
 #else
 	nrfx_err_t err;
-	nrf_ppi_channel_t ppi_ch;
+	nrfx_gppi_handle_t ppi_handle;
+	int rv;
 
 	for (int i = 0; i < GROUP_SIZE; ++i) {
 		uint8_t *gpiote_ch = &dev_data->gpiote_ch[i];
 
-		err = nrfx_ppi_channel_alloc(&ppi_ch);
-		if (err != NRFX_SUCCESS) {
-			LOG_ERR("Failed to allocate PPI channel.");
-			/* Do not bother with freeing resources allocated
-			 * so far. The application needs to be reconfigured
-			 * anyway.
-			 */
-			return -ENOMEM;
-		}
-
 		err = nrfx_gpiote_channel_alloc(&dev_config->gpiote, gpiote_ch);
 		if (err != NRFX_SUCCESS) {
 			LOG_ERR("Failed to allocate GPIOTE channel.");
@@ -463,12 +452,21 @@
 			return -ENOMEM;
 		}
 
-		nrf_ppi_channel_endpoint_setup(NRF_PPI, ppi_ch,
+		rv = nrfx_gppi_conn_alloc(
 			nrf_timer_event_address_get(dev_config->timer,
 				nrf_timer_compare_event_get(1 + i)),
 			nrf_gpiote_event_address_get(dev_config->gpiote.p_reg,
-				nrf_gpiote_out_task_get(*gpiote_ch)));
-		nrf_ppi_channel_enable(NRF_PPI, ppi_ch);
+				nrf_gpiote_out_task_get(*gpiote_ch)),
+			&ppi_handle);
+		if (rv < 0) {
+			LOG_ERR("Failed to allocate PPI channel.");
+			/* Do not bother with freeing resources allocated
+			 * so far. The application needs to be reconfigured
+			 * anyway.
+			 */
+			return rv;
+		}
+		nrfx_gppi_conn_enable(ppi_handle);
 	}
 #endif /* USE_PWM */
 

drivers/pwm/pwm_nrf_sw.c

@@ -72,8 +72,9 @@
 struct pwm_data {
 	uint32_t period_cycles;
 	uint32_t pulse_cycles[PWM_0_MAP_SIZE];
-	uint8_t ppi_ch[PWM_0_MAP_SIZE][PPI_PER_CH];
+	nrfx_gppi_handle_t ppi_h[PWM_0_MAP_SIZE][PPI_PER_CH];
 	uint8_t gpiote_ch[PWM_0_MAP_SIZE];
+	uint32_t ppi_ch_mask[PWM_0_MAP_SIZE];
 };
 
 static inline NRF_RTC_Type *pwm_config_rtc(const struct pwm_config *config)
@@ -126,11 +127,11 @@
 	NRF_RTC_Type *rtc = pwm_config_rtc(config);
 	NRF_GPIOTE_Type *gpiote;
 	struct pwm_data *data = dev->data;
-	uint32_t ppi_mask;
 	uint8_t active_level;
 	uint8_t psel_ch;
 	uint8_t gpiote_ch;
-	const uint8_t *ppi_chs;
+	const nrfx_gppi_handle_t *ppi_chs;
+	uint32_t src_d = nrfx_gppi_domain_id_get((USE_RTC ? (uint32_t)rtc : (uint32_t)timer));
 	int ret;
 
 	if (channel >= config->map_size) {
@@ -166,15 +167,13 @@
 	gpiote = config->gpiote[channel].p_reg;
 	psel_ch = config->psel_ch[channel];
 	gpiote_ch = data->gpiote_ch[channel];
-	ppi_chs = data->ppi_ch[channel];
+	ppi_chs = data->ppi_h[channel];
 
 	LOG_DBG("channel %u, period %u, pulse %u",
 		channel, period_cycles, pulse_cycles);
 
-	/* clear PPI used */
-	ppi_mask = BIT(ppi_chs[0]) | BIT(ppi_chs[1]) |
-		   (PPI_PER_CH > 2 ? BIT(ppi_chs[2]) : 0);
-	nrfx_gppi_channels_disable(ppi_mask);
+	/* disable PPI used */
+	nrfx_gppi_channels_disable(src_d, data->ppi_ch_mask[channel]);
 
 	active_level = (flags & PWM_POLARITY_INVERTED) ? 0 : 1;
 
@@ -278,13 +277,11 @@
 				nrf_rtc_compare_event_get(0));
 
 #if PPI_FORK_AVAILABLE
-		nrfx_gppi_fork_endpoint_setup(ppi_chs[1],
-					      clear_task_address);
+	nrfx_gppi_ep_attach(ppi_chs[1], clear_task_address);
 #else
-		nrfx_gppi_channel_endpoints_setup(ppi_chs[2],
-						  period_end_event_address,
-						  clear_task_address);
+	nrfx_gppi_ep_attach(ppi_chs[2], period_end_event_address);
+	nrfx_gppi_ep_attach(ppi_chs[2], clear_task_address);
 #endif
 	} else {
 		pulse_end_event_address =
 			nrf_timer_event_address_get(timer,
@@ -294,13 +291,13 @@
 				nrf_timer_compare_event_get(0));
 	}
 
-	nrfx_gppi_channel_endpoints_setup(ppi_chs[0],
-					  pulse_end_event_address,
-					  pulse_end_task_address);
-	nrfx_gppi_channel_endpoints_setup(ppi_chs[1],
-					  period_end_event_address,
-					  period_end_task_address);
-	nrfx_gppi_channels_enable(ppi_mask);
+	nrfx_gppi_ep_attach(ppi_chs[0], pulse_end_event_address);
+	nrfx_gppi_ep_attach(ppi_chs[0], pulse_end_task_address);
+
+	nrfx_gppi_ep_attach(ppi_chs[1], period_end_event_address);
+	nrfx_gppi_ep_attach(ppi_chs[1], period_end_task_address);
+
+	nrfx_gppi_channels_enable(src_d, data->ppi_ch_mask[channel]);
 
 	/* start timer, hence PWM */
 	if (USE_RTC) {
@@ -349,21 +346,32 @@
 	struct pwm_data *data = dev->data;
 	NRF_TIMER_Type *timer = pwm_config_timer(config);
 	NRF_RTC_Type *rtc = pwm_config_rtc(config);
+	uint32_t src_d = nrfx_gppi_domain_id_get((USE_RTC ? (uint32_t)rtc : (uint32_t)timer));
 
 	for (uint32_t i = 0; i < config->map_size; i++) {
 		nrfx_err_t err;
+		uint32_t dst_d = nrfx_gppi_domain_id_get((uint32_t)config->gpiote[i].p_reg);
+		int rv;
 
 		/* Allocate resources. */
 		for (uint32_t j = 0; j < PPI_PER_CH; j++) {
-			err = nrfx_gppi_channel_alloc(&data->ppi_ch[i][j]);
-			if (err != NRFX_SUCCESS) {
+			int ch;
+
+			rv = nrfx_gppi_domain_conn_alloc(src_d, dst_d, &data->ppi_h[i][j]);
+			if (rv < 0) {
 				/* Do not free allocated resource. It is a fatal condition,
 				 * system requires reconfiguration.
 				 */
 				LOG_ERR("Failed to allocate PPI channel");
-				return -ENOMEM;
+				return rv;
 			}
+			/* Enable connection but at the end disable channel on the source domain. */
+			nrfx_gppi_conn_enable(data->ppi_h[i][j]);
+			ch = nrfx_gppi_domain_channel_get(data->ppi_h[i][j], src_d);
+			__ASSERT_NO_MSG(ch >= 0);
+			data->ppi_ch_mask[i] |= BIT(ch);
 		}
+		nrfx_gppi_channels_disable(src_d, data->ppi_ch_mask[i]);
 
 		err = nrfx_gpiote_channel_alloc(&config->gpiote[i],
 						&data->gpiote_ch[i]);

drivers/serial/uart_nrfx_uarte.c

@@ -229,8 +229,8 @@
 	uint8_t *anomaly_byte_dst;
 	uint8_t anomaly_byte;
 #endif
+	nrfx_gppi_handle_t ppi_h;
 	uint8_t bounce_idx;
-	uint8_t ppi_ch;
 	bool in_irq;
 	bool discard_fifo;
 };
@@ -259,7 +259,7 @@
 	int32_t timeout_slab; /* rx_timeout divided by RX_TIMEOUT_DIV */
 	int32_t timeout_left; /* Current time left until user callback */
 	union {
-		uint8_t ppi;
+		nrfx_gppi_handle_t ppi;
 		uint32_t cnt;
 	} cnt;
 	/* Flag to ensure that RX timeout won't be executed during ENDRX ISR */
@@ -311,7 +311,7 @@
 	atomic_val_t poll_out_lock;
 	atomic_t flags;
 #ifdef UARTE_ENHANCED_POLL_OUT
-	uint8_t ppi_ch_endtx;
+	nrfx_gppi_handle_t ppi_h_endtx;
 #endif
 };
 
@@ -1083,15 +1083,14 @@
 
 		nrfx_timer_clear(&data->timer);
 
-		ret = nrfx_gppi_channel_alloc(&data->async->rx.cnt.ppi);
-		if (ret != NRFX_SUCCESS) {
+		ret = nrfx_gppi_conn_alloc(evt_addr, tsk_addr, &data->async->rx.cnt.ppi);
+		if (ret < 0) {
 			LOG_ERR("Failed to allocate PPI Channel");
 			nrfx_timer_uninit(&data->timer);
-			return -EINVAL;
+			return ret;
 		}
 
-		nrfx_gppi_channel_endpoints_setup(data->async->rx.cnt.ppi, evt_addr, tsk_addr);
-		nrfx_gppi_channels_enable(BIT(data->async->rx.cnt.ppi));
+		nrfx_gppi_conn_enable(data->async->rx.cnt.ppi);
 	} else {
 		nrf_uarte_int_enable(uarte, NRF_UARTE_INT_RXDRDY_MASK);
 	}
@@ -1722,18 +1721,17 @@
 						NRF_UARTE_INT_RXTO_MASK;
 	uint32_t evt = nrf_uarte_event_address_get(cfg->uarte_regs, NRF_UARTE_EVENT_RXDRDY);
 	uint32_t tsk = nrf_timer_task_address_get(cfg->timer_regs, NRF_TIMER_TASK_COUNT);
-	nrfx_err_t ret;
+	int ret;
 
 	nrf_timer_mode_set(cfg->timer_regs, NRF_TIMER_MODE_COUNTER);
 	nrf_timer_bit_width_set(cfg->timer_regs, NRF_TIMER_BIT_WIDTH_32);
 
-	ret = nrfx_gppi_channel_alloc(&cbwt_data->ppi_ch);
-	if (ret != NRFX_SUCCESS) {
-		return -ENOMEM;
+	ret = nrfx_gppi_conn_alloc(evt, tsk, &cbwt_data->ppi_h);
+	if (ret < 0) {
+		return ret;
 	}
 
-	nrfx_gppi_channel_endpoints_setup(cbwt_data->ppi_ch, evt, tsk);
-	nrfx_gppi_channels_enable(BIT(cbwt_data->ppi_ch));
+	nrfx_gppi_conn_enable(cbwt_data->ppi_h);
 
 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
 	cbwt_data->bounce_buf_swap_len = cfg->bounce_buf_swap_len;
@@ -3142,18 +3140,17 @@
 static int endtx_stoptx_ppi_init(NRF_UARTE_Type *uarte,
 				 struct uarte_nrfx_data *data)
 {
-	nrfx_err_t ret;
+	int ret;
 
-	ret = nrfx_gppi_channel_alloc(&data->ppi_ch_endtx);
-	if (ret != NRFX_SUCCESS) {
+	ret = nrfx_gppi_conn_alloc(
+		nrf_uarte_event_address_get(uarte, NRF_UARTE_EVENT_ENDTX),
+		nrf_uarte_task_address_get(uarte, NRF_UARTE_TASK_STOPTX), &data->ppi_h_endtx);
+	if (ret < 0) {
 		LOG_ERR("Failed to allocate PPI Channel");
-		return -EIO;
+		return ret;
 	}
 
-	nrfx_gppi_channel_endpoints_setup(data->ppi_ch_endtx,
-		nrf_uarte_event_address_get(uarte, NRF_UARTE_EVENT_ENDTX),
-		nrf_uarte_task_address_get(uarte, NRF_UARTE_TASK_STOPTX));
-	nrfx_gppi_channels_enable(BIT(data->ppi_ch_endtx));
+	nrfx_gppi_conn_enable(data->ppi_h_endtx);
 
 	return 0;
 }

drivers/timer/Kconfig.nrf_rtc

@@ -9,7 +9,7 @@ config NRF_RTC_TIMER
 	depends on SOC_COMPATIBLE_NRF
 	select TICKLESS_CAPABLE
 	select SYSTEM_TIMER_HAS_DISABLE_SUPPORT
-	select NRFX_PPI if SOC_NRF52832
+	select NRFX_GPPI if SOC_NRF52832
 	depends on !$(dt_nodelabel_enabled,rtc1)
 	help
 	  This module implements a kernel device driver for the nRF Real Time