[nrf fromtree] boards: nrf9280pdk: Merge cpuapp iron variant into the base variant

boards/nordic/nrf9280pdk/Kconfig.defconfig

@@ -4,17 +4,6 @@
 config HW_STACK_PROTECTION
 	default ARCH_HAS_STACK_PROTECTION
 
-if BOARD_NRF9280PDK_NRF9280_CPUAPP
-
-config BT_HCI_IPC
-	default y if BT
-
-endif # BOARD_NRF9280PDK_NRF9280_CPUAPP
-
-if BOARD_NRF9280PDK_NRF9280_CPURAD
-
-endif # BOARD_NRF9280PDK_NRF9280_CPURAD
-
 if BOARD_NRF9280PDK_NRF9280_CPUPPR
 
 # As PPR has limited memory most of tests does not fit with asserts enabled.
@@ -23,12 +12,12 @@ config ASSERT
 
 endif # BOARD_NRF9280PDK_NRF9280_CPUPPR
 
-if BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON
+if BOARD_NRF9280PDK_NRF9280_CPUAPP
 
 config ROM_START_OFFSET
 	default 0x800 if BOOTLOADER_MCUBOOT
 
 config FLASH_LOAD_OFFSET
 	default $(dt_nodelabel_reg_addr_hex,cpuapp_boot_partition) if !USE_DT_CODE_PARTITION
 
-endif # BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON
+endif # BOARD_NRF9280PDK_NRF9280_CPUAPP

boards/nordic/nrf9280pdk/Kconfig.nrf9280pdk

@@ -2,9 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_NRF9280PDK
-	select SOC_NRF9280_CPUAPP if (BOARD_NRF9280PDK_NRF9280_CPUAPP || \
-				       BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON)
+	select SOC_NRF9280_CPUAPP if BOARD_NRF9280PDK_NRF9280_CPUAPP
 	select SOC_NRF9280_CPURAD if BOARD_NRF9280PDK_NRF9280_CPURAD
 	select SOC_NRF9280_CPUPPR if (BOARD_NRF9280PDK_NRF9280_CPUPPR || \
 				       BOARD_NRF9280PDK_NRF9280_CPUPPR_XIP)
-	select SOC_NRF9280_IRON if BOARD_NRF9280PDK_NRF9280_CPUAPP_IRON

boards/nordic/nrf9280pdk/board.yml

@@ -7,8 +7,6 @@ board:
     variants:
     - name: xip
       cpucluster: cpuppr
-    - name: iron
-      cpucluster: cpuapp
   revision:
     format: major.minor.patch
     default: 0.2.0

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi

@@ -7,17 +7,17 @@
 / {
 	ipc {
 		cpusec_cpuapp_ipc: ipc-1-2 {
-			compatible = "zephyr,ipc-icmsg";
+			compatible = "nordic,ironside-call";
 			status = "disabled";
-			dcache-alignment = <32>;
+			memory-region = <&cpusec_cpuapp_ipc_shm>;
 			mboxes = <&cpusec_bellboard 12>,
 				 <&cpuapp_bellboard 0>;
 		};
 
 		cpusec_cpurad_ipc: ipc-1-3 {
-			compatible = "zephyr,ipc-icmsg";
+			compatible = "nordic,ironside-call";
 			status = "disabled";
-			dcache-alignment = <32>;
+			memory-region = <&cpusec_cpurad_ipc_shm>;
 			mboxes = <&cpusec_bellboard 18>,
 				 <&cpurad_bellboard 0>;
 		};
@@ -33,6 +33,7 @@
 		cpuapp_cpusys_ipc: ipc-2-12 {
 			compatible = "zephyr,ipc-icmsg";
 			status = "disabled";
+			unbound = "enable";
 			dcache-alignment = <32>;
 			mboxes = <&cpuapp_bellboard 6>,
 				 <&cpusys_vevif 12>;

boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi

@@ -38,14 +38,6 @@
 			#size-cells = <1>;
 			ranges = <0x0 0x2f012000 0x81000>;
 
-			cpusec_cpuapp_ipc_shm: memory@0 {
-				reg = <0x0 DT_SIZE_K(2)>;
-			};
-
-			cpuapp_cpusec_ipc_shm: memory@800 {
-				reg = <0x800 DT_SIZE_K(2)>;
-			};
-
 			cpuapp_data: memory@1000 {
 				reg = <0x1000 DT_SIZE_K(512)>;
 			};
@@ -98,12 +90,27 @@
 			};
 		};
 
-		cpuapp_cpusys_ipc_shm: memory@2f88fce0 {
-			reg = <0x2f88fce0 0x80>;
+		/* Workaround for a data cache related issue with SoC1.1, use secure addresses
+		 * for cpuapp_cpusys_ipc_shm, cpusys_cpuapp_ipc_shm and cpusec_cpuapp_ipc_shm.
+		 */
+		cpuapp_cpusys_ipc_shm: memory@3f88f600 {
+			reg = <0x3f88f600 0x80>;
 		};
 
-		cpusys_cpuapp_ipc_shm: memory@2f88fd60 {
-			reg = <0x2f88fd60 0x80>;
+		cpusys_cpuapp_ipc_shm: memory@3f88f680 {
+			reg = <0x3f88f680 0x80>;
+		};
+
+		cpusec_cpuapp_ipc_shm: memory@3f88fb80 {
+			reg = <0x3f88fb80 0x80>;
+		};
+
+		cpuapp_ironside_se_event_report: memory@2f88fc00 {
+			reg = <0x2f88fc00 0x100>;
+		};
+
+		cpuapp_ironside_se_boot_report: memory@2f88fd00 {
+			reg = <0x2f88fd00 0x200>;
 		};
 
 		cpurad_cpusys_ipc_shm: memory@2f88fe00 {
@@ -178,57 +185,64 @@
 };
 
 &mram1x {
-	cpurad_rx_partitions: cpurad-rx-partitions {
-		compatible = "nordic,owned-partitions", "fixed-partitions";
-		status = "disabled";
-		nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RXS>;
+	partitions {
+		compatible = "fixed-partitions";
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpurad_slot0_partition: partition@402000 {
-			reg = <0x402000 DT_SIZE_K(256)>;
+		cpuapp_boot_partition: partition@312000 {
+			reg = <0x312000 DT_SIZE_K(64)>;
 		};
-	};
 
-	cpuapp_rx_partitions: cpuapp-rx-partitions {
-		compatible = "nordic,owned-partitions", "fixed-partitions";
-		status = "disabled";
-		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
-		#address-cells = <1>;
-		#size-cells = <1>;
+		cpuapp_slot0_partition: partition@322000 {
+			reg = <0x322000 DT_SIZE_K(336)>;
+		};
 
-		cpuapp_slot0_partition: partition@442000 {
-			reg = <0x442000 DT_SIZE_K(1024)>;
+		cpuapp_slot1_partition: partition@376000 {
+			reg = <0x376000 DT_SIZE_K(440)>;
 		};
 
-		cpuppr_code_partition: partition@542000 {
-			reg = <0x542000 DT_SIZE_K(64)>;
+		cpuppr_code_partition: partition@3E4000 {
+			reg = <0x3E4000 DT_SIZE_K(64)>;
 		};
-	};
 
-	cpuapp_rw_partitions: cpuapp-rw-partitions {
-		compatible = "nordic,owned-partitions", "fixed-partitions";
-		status = "disabled";
-		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
-		#address-cells = <1>;
-		#size-cells = <1>;
+		cpuflpr_code_partition: partition@3F4000 {
+			reg = <0x3F4000 DT_SIZE_K(48)>;
+		};
 
-		dfu_partition: partition@600000 {
-			reg = <0x600000 DT_SIZE_K(512)>;
+		cpurad_slot0_partition: partition@400000 {
+			reg = <0x400000 DT_SIZE_K(336)>;
 		};
 
-		storage_partition: partition@680000 {
-			reg = <0x680000 DT_SIZE_K(24)>;
+		cpurad_slot1_partition: partition@454000 {
+			reg = <0x454000 DT_SIZE_K(336)>;
 		};
-	};
 
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
+		storage_partition: partition@600000 {
+			reg = <0x600000 DT_SIZE_K(40)>;
+		};
 
 		periphconf_partition: partition@60a000 {
 			reg = <0x60a000 DT_SIZE_K(8)>;
 		};
+
+		/* 0x60c000 was chosen for secure_storage_partition such that
+		 * it resides in the beginning of MRAM11 in storage partition.
+		 */
+		secure_storage_partition: partition@60c000 {
+			compatible = "fixed-subpartitions";
+			reg = <0x60c000 DT_SIZE_K(8)>;
+			ranges = <0x0 0x60c000 0x2000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cpuapp_crypto_partition: partition@0 {
+				reg = <0x0 DT_SIZE_K(4)>;
+			};
+
+			cpuapp_its_partition: partition@1000 {
+				reg = <0x1000 DT_SIZE_K(4)>;
+			};
+		};
 	};
 };