[Backport ncs-v3.2-branch] [fromtree] GPPI updates

soc/nordic/common/Kconfig.peripherals

@@ -42,7 +42,8 @@ config HAS_HW_NRF_DCNF
 	def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_DCNF))
 
 config HAS_HW_NRF_DPPIC
-	def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_DPPIC))
+	def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_DPPIC)) || \
+		 $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_DPPIC_LOCAL))
 
 config HAS_HW_NRF_ECB
 	def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_ECB))

soc/nordic/common/gppi_init.c

@@ -7,6 +7,8 @@
 #include <helpers/nrfx_gppi.h>
 #if defined(NRFX_GPPI_MULTI_DOMAIN) && !defined(NRFX_GPPI_FIXED_CONNECTIONS)
 #include <soc/interconnect/nrfx_gppi_lumos.h>
+#elif defined(CONFIG_SOC_NRF54H20_CPURAD)
+#include <nrfx_gppi_cpurad.h>
 #endif
 
 static int gppi_init(void)
@@ -47,6 +49,21 @@ static int gppi_init(void)
 			NRFX_BIT_MASK(DPPIC20_GROUP_NUM_SIZE) & ~NRFX_DPPI20_GROUPS_USED);
 	nrfx_gppi_groups_init(NRFX_GPPI_NODE_DPPIC30,
 			NRFX_BIT_MASK(DPPIC30_GROUP_NUM_SIZE) & ~NRFX_DPPI30_GROUPS_USED);
+#elif defined(CONFIG_SOC_NRF54H20_CPURAD)
+	gppi_instance.routes = nrfx_gppi_routes_get();
+	gppi_instance.route_map = nrfx_gppi_route_map_get();
+	gppi_instance.nodes = nrfx_gppi_nodes_get();
+
+	nrfx_gppi_channel_init(NRFX_GPPI_NODE_DPPIC020,
+			NRFX_BIT_MASK(DPPIC020_CH_NUM_SIZE) & ~NRFX_DPPI020_CHANNELS_USED);
+	nrfx_gppi_channel_init(NRFX_GPPI_NODE_DPPIC030,
+			NRFX_BIT_MASK(DPPIC030_CH_NUM_SIZE) & ~NRFX_DPPI030_CHANNELS_USED);
+	nrfx_gppi_channel_init(NRFX_GPPI_NODE_PPIB020_030,
+			NRFX_BIT_MASK(PPIB020_NTASKSEVENTS_SIZE));
+	nrfx_gppi_groups_init(NRFX_GPPI_NODE_DPPIC020,
+			NRFX_BIT_MASK(DPPIC020_GROUP_NUM_SIZE) & ~NRFX_DPPI020_GROUPS_USED);
+	nrfx_gppi_groups_init(NRFX_GPPI_NODE_DPPIC030,
+			NRFX_BIT_MASK(DPPIC030_GROUP_NUM_SIZE) & ~NRFX_DPPI030_GROUPS_USED);
 #else
 #error "Not supported"
 #endif

soc/nordic/nrf54h/CMakeLists.txt

@@ -17,6 +17,10 @@ if(NOT CONFIG_SOC_NRF54H20_PM_S2RAM_OVERRIDE)
   zephyr_library_sources_ifdef(CONFIG_PM_S2RAM pm_s2ram.c)
 endif()
 
+if(CONFIG_NRFX_GPPI AND NOT CONFIG_NRFX_GPPI_V1)
+  zephyr_library_sources_ifdef(CONFIG_SOC_NRF54H20_CPURAD nrfx_gppi_cpurad.c)
+endif()
+
 zephyr_include_directories(.)
 
 # Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes

soc/nordic/nrf54h/nrfx_gppi_cpurad.c

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "nrfx_gppi_cpurad.h"
+
+static nrfx_atomic_t channels[NRFX_GPPI_NODE_COUNT];
+static nrfx_atomic_t group_channels[NRFX_GPPI_NODE_DPPI_COUNT];
+
+static const nrfx_gppi_node_t nodes[] = {
+	NRFX_GPPI_DPPI_NODE_DEFINE(020, NRFX_GPPI_NODE_DPPIC020),
+	NRFX_GPPI_DPPI_NODE_DEFINE(030, NRFX_GPPI_NODE_DPPIC030),
+	NRFX_GPPI_PPIB_NODE_DEFINE(020, 030),
+};
+
+static const nrfx_gppi_route_t dppi_routes[] = {
+	NRFX_GPPI_ROUTE_DEFINE("slow_rad", (&nodes[NRFX_GPPI_NODE_DPPIC020])),
+	NRFX_GPPI_ROUTE_DEFINE("fast_rad", (&nodes[NRFX_GPPI_NODE_DPPIC030])),
+	NRFX_GPPI_ROUTE_DEFINE("slow_fast_rad",
+			(&nodes[NRFX_GPPI_NODE_DPPIC020],
+			 &nodes[NRFX_GPPI_NODE_PPIB020_030],
+			 &nodes[NRFX_GPPI_NODE_DPPIC030])),
+};
+
+static const nrfx_gppi_route_t *slow_rad_routes[] = {
+	&dppi_routes[0], &dppi_routes[2]
+};
+
+static const nrfx_gppi_route_t *fast_rad_routes[] = {
+	&dppi_routes[1]
+};
+
+static const nrfx_gppi_route_t **dppi_route_map[] = {
+	slow_rad_routes, fast_rad_routes
+};
+
+uint32_t nrfx_gppi_domain_id_get(uint32_t addr)
+{
+	uint32_t domain = (addr >> 24) & BIT_MASK(3);
+	uint32_t bus = (addr >> 16) & BIT_MASK(8);
+
+	(void)domain;
+	__ASSERT_NO_MSG(domain == 3);
+	switch (bus) {
+	case 2:
+		return NRFX_GPPI_NODE_DPPIC020;
+	case 3:
+		return NRFX_GPPI_NODE_DPPIC030;
+	default:
+		__ASSERT_NO_MSG(0);
+		return 0;
+	}
+}
+
+const nrfx_gppi_route_t ***nrfx_gppi_route_map_get(void)
+{
+	return dppi_route_map;
+}
+
+const nrfx_gppi_route_t *nrfx_gppi_routes_get(void)
+{
+	return dppi_routes;
+}
+
+const nrfx_gppi_node_t *nrfx_gppi_nodes_get(void)
+{
+	return nodes;
+}
+
+void nrfx_gppi_channel_init(nrfx_gppi_node_id_t node_id, uint32_t ch_mask)
+{
+	NRFX_ASSERT(node_id < NRFX_GPPI_NODE_COUNT);
+
+	*nodes[node_id].generic.p_channels = ch_mask;
+}
+
+void nrfx_gppi_groups_init(nrfx_gppi_node_id_t node_id, uint32_t group_mask)
+{
+	NRFX_ASSERT(node_id < NRFX_GPPI_NODE_DPPI_COUNT);
+
+	*nodes[node_id].dppi.p_group_channels = group_mask;
+}

soc/nordic/nrf54h/nrfx_gppi_cpurad.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SOC_NORDIC_NRF54H_NRFX_GPPI_CPURAD_H_
+#define SOC_NORDIC_NRF54H_NRFX_GPPI_CPURAD_H_
+
+#include <helpers/nrfx_gppi_routes.h>
+
+typedef enum {
+	NRFX_GPPI_NODE_DPPIC020,
+	NRFX_GPPI_NODE_DPPIC030,
+	NRFX_GPPI_NODE_DPPI_COUNT,
+	NRFX_GPPI_NODE_PPIB020_030 = NRFX_GPPI_NODE_DPPI_COUNT,
+	NRFX_GPPI_NODE_COUNT
+} nrfx_gppi_node_id_t;
+
+const nrfx_gppi_route_t ***nrfx_gppi_route_map_get(void);
+const nrfx_gppi_route_t *nrfx_gppi_routes_get(void);
+const nrfx_gppi_node_t *nrfx_gppi_nodes_get(void);
+void nrfx_gppi_channel_init(nrfx_gppi_node_id_t node_id, uint32_t ch_mask);
+void nrfx_gppi_groups_init(nrfx_gppi_node_id_t node_id, uint32_t group_mask);
+
+#endif /* SOC_NORDIC_NRF54H_NRFX_GPPI_CPURAD_H_ */

west.yml

@@ -200,7 +200,7 @@ manifest:
       groups:
         - hal
     - name: hal_nordic
-      revision: e891e1cda4db109c6816cc929dda4f6a18e3e1bc
+      revision: 0dbbf4794156ca09dc2d4bad8c42dcdb54acd662
       path: modules/hal/nordic
       groups:
         - hal