Conga smx95 dev

CRT.crt

@@ -0,0 +1,19 @@
+-----BEGIN CERTIFICATE-----
+MIIC/zCCAeegAwIBAgIUfUJbx92qBtzGeQaRA7hSzKRlhWUwDQYJKoZIhvcNAQEL
+BQAwDjEMMAoGA1UEAwwDQ1JUMCAXDTI0MTExNTAzNTIzOVoYDzIxMjQxMDIyMDM1
+MjM5WjAOMQwwCgYDVQQDDANDUlQwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEK
+AoIBAQC13qPs95d+aGuqlmA/RlmuV7/5cwBoutJscXsVPUTdlbOc5DKZJLduOD6y
+g7ZVE4qJCfCYbzcD6CyW3LvkSxE0zsOmh5wmXjIWKj0qtHiwqUuMkuF5NCjZI1mU
+LNnT1BSL/OEW1++zy7sXTGtjmJ09e2OT2j0FM0w/KaCQGZuiZuAehreamXPaFM/Z
+fsKYVUFZas1vjJTIjLsN3CK0X4CtwRdX6Uy3FYIhbsnu2up6PX1QQczXr2EoRzmN
+Ssbu+V7u9umNDx4sSY49BR9+yk0/0CpKiG/dPW4/lnQpjhv4QduEQ5FSsrVcyXrt
+wvzBZuroZOraDKQTgyuJysOqfCEPAgMBAAGjUzBRMB0GA1UdDgQWBBS+oJb1BMP3
+9TbaO+8QLQcgdW8l/DAfBgNVHSMEGDAWgBS+oJb1BMP39TbaO+8QLQcgdW8l/DAP
+BgNVHRMBAf8EBTADAQH/MA0GCSqGSIb3DQEBCwUAA4IBAQA+l1aPImEa8dqrLHRc
+bV/upn95UxFX4ZZmOx8B11UUlhABjHlOb7BDSnxU3yP21qPx35FMYUPAJ00hQKvY
+jJKzxHXQ5PO7GcUO/7UJ3BAB1bRLrtrbE/Mpn/KQtf4uTyuL+06XKFtxLedcko0z
+Lg39QuUqO+MNtCFghyjJy2JQcxsTTVYt2G8MWwfJrkQIcUvd9yFdFZUzicodX7gB
+HWtryN44jagfwa/8BGt1etmaVCTE8scy5CDxmED+Hvsrj//M3OydL8GuVht/fgxE
+aTONVbiAYuBmPwUh7lODsboMX0KoOT4kKFIh9GUXXXXOjTTmmcuMsvB7aRxFMLIj
+KKOu
+-----END CERTIFICATE-----

CRT.key

@@ -0,0 +1,28 @@
+-----BEGIN PRIVATE KEY-----
+MIIEvAIBADANBgkqhkiG9w0BAQEFAASCBKYwggSiAgEAAoIBAQC13qPs95d+aGuq
+lmA/RlmuV7/5cwBoutJscXsVPUTdlbOc5DKZJLduOD6yg7ZVE4qJCfCYbzcD6CyW
+3LvkSxE0zsOmh5wmXjIWKj0qtHiwqUuMkuF5NCjZI1mULNnT1BSL/OEW1++zy7sX
+TGtjmJ09e2OT2j0FM0w/KaCQGZuiZuAehreamXPaFM/ZfsKYVUFZas1vjJTIjLsN
+3CK0X4CtwRdX6Uy3FYIhbsnu2up6PX1QQczXr2EoRzmNSsbu+V7u9umNDx4sSY49
+BR9+yk0/0CpKiG/dPW4/lnQpjhv4QduEQ5FSsrVcyXrtwvzBZuroZOraDKQTgyuJ
+ysOqfCEPAgMBAAECggEAA+gmTasHQkFm/Vv2nFVcDCk5aAKRly5a4oEmO49nNnqx
+SDpaCz0lLZp1X6tW/t6JGCbdAsFHhW923xTFz9fRpPiYw6/fvwPrVTDkwyaWUyEy
+jMYDpEa7u+e3qb20PjSCQ9GTr5nFk0SvSQcCEDp74jwPfbfEniMlzP44GJsG41xY
+xmhijeCsc8nplY0YVieZNu3l2L2Ly2rfu8SsQm3i9ssCWDX6A2kaq4Qzj0S9g502
+qGjQtp7sCVQWgfFglOZZJZgkvSPcJgqQrcJm2KbMhpDW3arl3J7lWiMt48p9xxXG
+VCjjNrWKwA/PYf+SRqE7Zw2gqt1/LNKhhK4NU6MoTQKBgQDhOxi8SZvXYJkBj5sk
+6I+de1blA0f/M5e7BtTRrVWKXB2KDrToVEsxu7LxrABJl6VgCzwDVFVhywVIemy4
+uc7p9g3wPO6u5sqNkgb39ktKHT5R51P8OoVpJnQ4/hAJimrhJoQJnN8Rl/pLc7vK
+zkEUPiQJ0S4R6GSagER5dUnzKwKBgQDOtxedYPN9S77Gt/XhhyxINxkhjlogPcO5
+cqJUbv6OVaTrxbTZ9z20/lIXVa41SvWHzio5Q+UqzwlMUkJtMufVoWwzmgbNqgt+
+kC/mD6rk8aYpwnDgtKyRp3prHtDL7Abojs44trB9zlhNfBjnqXiR2PNQiLQDXbyF
+8vayJ8XnrQKBgBUZ8EtTqiIXjr4yshpXH31lnNJ/6DLkpoaDMVUjpCv+TVYt4o0R
+uKnEKBO0RaKfboL9CnZVZFpxJuGPdrgn0FbjEpM7YjFIthllYPnCPXOIIdqSja/H
+28/qJmFgjCgYq8LEVQKBi/SeBHklMqbhg/9dgwrYajSLTUGcWs32SyNZAoGAQtV1
+oB+Jefg0bUFrEQjIK20NBgllYEk378x9aXkdel18XfJlH5fNbqhPWFYOZhKfQdJJ
+Wox2GponsnJiIbY0uKBhQGnLS1FwN/JcWjC0myL6C0RfhHdF2C3i6aFj9pqQPT52
+tGV0uKgvapX142iqn9UaDe607OWwn0pHsqAjX10CgYBCjAxwlzOyTOwETxnIdAM3
+4q8olAmm54vmRnW+qoF1VInAtNLR5/aGwPbh2zSYRp6n+t5zshFEmRzYQtLhHuiV
+ckc6qytxlpA5SdU8XEvkIL1TmelDaG4YrVmhhpfsAJynZ9V541pXZ/tAd40CiUBK
+wi9he9qKzUKcSwAKQXr3Pg==
+-----END PRIVATE KEY-----

Kconfig

@@ -541,7 +541,7 @@ config SYS_LOAD_ADDR
 	default 0x22000000 if MACH_SUN9I
 	default 0x42000000 if ARCH_SUNXI
 	default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
-	default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
+	default 0x80800000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
 	default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
 	default 0x80800000 if ARCH_MX7
 	default 0x90000000 if FSL_LSCH2 || FSL_LSCH3

Makefile

@@ -865,6 +865,7 @@ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
 libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
 libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/
 libs-y += drivers/usb/cdns3/
+libs-y += drivers/usb/imx/
 libs-y += drivers/usb/dwc3/
 libs-y += drivers/usb/common/
 libs-y += drivers/usb/emul/

arch/Kconfig.nxp

@@ -178,6 +178,12 @@ config FSL_USE_PCA9547_MUX
 	help
 	 This option enables the PCA9547 I2C mux on Freescale boards.
 
+config USB_TCPC
+	bool "USB Typec port controller simple driver"
+	default n
+	help
+	 Enable USB type-c port controller (TCPC) driver
+
 config VID
 	bool "Enable Freescale VID"
 	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)

arch/arm/Kconfig

@@ -20,9 +20,14 @@ config ARM64_CRC32
 	  not be present on all ARMv8.0, but is always present on ARMv8.1 and
 	  newer.
 
+config ARM64_NEON
+	bool "Enable support for NEON instruction"
+	default n
+
 config COUNTER_FREQUENCY
 	int "Timer clock frequency"
 	depends on ARM64 || CPU_V7A
+	default 1000000 if IMX8ULP
 	default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
 	default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
 			ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
@@ -894,6 +899,9 @@ config ARCH_IMX8ULP
 	select GPIO_EXTRA_HEADER
 	select MISC
 	select IMX_ELE
+	select SYS_FSL_HAS_SEC
+	select SYS_FSL_SEC_LE
+	select SYS_FSL_SEC_COMPAT_4
 	imply CMD_DM
 
 config ARCH_IMX9

arch/arm/Makefile

@@ -17,7 +17,11 @@ arch-$(CONFIG_CPU_V7A)		=$(call cc-option, -march=armv7-a, \
 arch-$(CONFIG_CPU_V7M)		=-march=armv7-m
 arch-$(CONFIG_CPU_V7R)		=-march=armv7-r
 ifeq ($(CONFIG_ARM64_CRC32),y)
+ifeq ($(CONFIG_ARM64_NEON),y)
+arch-$(CONFIG_ARM64)		=-march=armv8-a+crc+crypto
+else
 arch-$(CONFIG_ARM64)		=-march=armv8-a+crc
+endif
 else
 arch-$(CONFIG_ARM64)		=-march=armv8-a
 endif
@@ -30,6 +34,10 @@ else
 arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
 endif
 
+ifneq ($(CONFIG_ARCH_IMX8)$(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8ULP),)
+arch-y += -mgeneral-regs-only
+endif
+
 # Evaluate arch cc-option calls now
 arch-y := $(arch-y)
 

arch/arm/config.mk

@@ -158,6 +158,10 @@ OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
 endif
 
 ifdef CONFIG_MACH_IMX
+ifdef CONFIG_IMX_M4_BIND
+OBJCOPYFLAGS += -j .firmware_image
+endif
+
 ifneq ($(CONFIG_IMX_CONFIG),"")
 ifdef CONFIG_SPL
 ifndef CONFIG_SPL_BUILD

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -135,6 +135,7 @@ config ARCH_LS1046A
 	select SYS_I2C_MXC_I2C2 if !DM_I2C
 	select SYS_I2C_MXC_I2C3 if !DM_I2C
 	select SYS_I2C_MXC_I2C4 if !DM_I2C
+	select RESV_RAM if SYS_DPAA_QBMAN
 	imply ID_EEPROM
 	imply SCSI
 	imply SCSI_AHCI

arch/arm/cpu/armv8/fsl-layerscape/Makefile

@@ -7,6 +7,7 @@ obj-y += lowlevel.o
 obj-y += soc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o spintable.o
+obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 endif
 obj-$(CONFIG_SPL) += spl.o

arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c

@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021-2022 NXP
+ */
+#include <common.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/sizes.h>
+#include "dt_optee.h"
+
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd)
+{
+	int ret = 0;
+
+	/*
+	 * No BL32_BASE passed means no TEE running, so no
+	 * need to add optee node in dts
+	 */
+	if (!rom_pointer[0]) {
+		debug("No BL32_BASE passed means no TEE running\n");
+		return ret;
+	}
+
+	if (rom_pointer[2]) {
+		debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]);
+		ret = fdt_check_header((void *)rom_pointer[2]);
+		if (ret == 0) {
+			/* Copy the fdt overlay to next 1M and use copied overlay */
+			memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2],
+			       fdt_totalsize((void *)rom_pointer[2]));
+			ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M));
+			if (ret == 0) {
+				debug("Overlay applied with success");
+				fdt_pack(fdt);
+			}
+		} else {
+			printf("DTB overlay not present, exiting without applying\n");
+			ret = 0;
+		}
+	}
+	return ret;
+}

arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+#ifndef __DT_OPTEE_H__
+#define __DT_OPTEE_H__
+
+extern unsigned long rom_pointer[];
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd);
+#endif

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -31,6 +31,7 @@
 #endif
 #include <asm/arch/speed.h>
 #include <fsl_qbman.h>
+#include "dt_optee.h"
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -671,6 +672,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	fdt_fixup_bportals(blob);
 	fdt_fixup_qportals(blob);
+
+	fdt_fixup_qbman_reserved_mem(blob);
+
 	do_fixup_by_compat_u32(blob, "fsl,qman",
 			       "clock-frequency", get_qman_freq(), 1);
 #endif
@@ -697,3 +701,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_ecam(blob);
 #endif
 }
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	return ft_add_optee_overlay(blob, bd);
+#else
+	return 0;
+#endif
+}
+#endif

arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 32
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+	/* The firmware provided FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+
+	ldr	x1, =save_boot_params_ret
+	br	x1

arch/arm/cpu/u-boot.lds

@@ -176,6 +176,22 @@ SECTIONS
 		*(.__image_copy_end)
 	}
 
+#ifdef CONFIG_IMX_M4_BIND
+	.firmware_image_start : {
+                *(.__firmware_image_start)
+        }
+
+	.firmware_image : {
+		KEEP(*(.firmware_image))
+        }
+
+	.firmware_image_end : {
+                *(.__firmware_image_end)
+        }
+
+	. = ALIGN(4);
+#endif
+
 	.rel_dyn_start :
 	{
 		*(.__rel_dyn_start)