Set up mod support for running headless

object-Object · object-Object · commit 07fd36c71ba2 · 2025-07-15T01:43:32.000-04:00
diff --git a/mod/assets/scripts/main.js b/mod/assets/scripts/main.js
@@ -107,4 +107,85 @@ global.override.block(LogicBlock, {
     },
 });
 
+let activeProcessors = [];
+
+global.mlogv32 = {
+    loadSchematic: (/** @type {string} */ arg) => {
+        const [path, xRaw, yRaw, cpuXOffsetRaw, cpuYOffsetRaw, address, portRaw] = arg.split(" ");
+        const x = parseFloat(xRaw);
+        const y = parseFloat(yRaw);
+        const cpuXOffset = parseFloat(cpuXOffsetRaw);
+        const cpuYOffset = parseFloat(cpuYOffsetRaw);
+        const port = parseInt(portRaw);
+        if (
+            !path.length ||
+            isNaN(x) ||
+            isNaN(y) ||
+            isNaN(cpuXOffset) ||
+            isNaN(cpuYOffset) ||
+            isNaN(port) ||
+            port < 0 ||
+            port > 65535
+        ) {
+            Log.err("Invalid arguments.");
+            return;
+        }
+
+        /** @type {Fi} */
+        let file;
+        if (path[0] == "/") {
+            file = Core.files.absolute(path);
+        } else {
+            file = Core.files.local(path);
+        }
+
+        Log.info("Loading schematic: " + file);
+        const schem = Schematics.read(file);
+
+        Log.info("Placing schematic.");
+        Schematics.place(
+            schem,
+            x + schem.width / 2,
+            y + schem.height / 2,
+            Vars.state.rules.defaultTeam,
+            true
+        );
+
+        const cpuX = x + cpuXOffset;
+        const cpuY = cpuYOffset >= 0 ? y + cpuYOffset : y + schem.height + cpuYOffset;
+        Log.info("CPU position: " + cpuX + "," + cpuY);
+
+        const build = Vars.world.build(cpuX, cpuY);
+        if (build == null) {
+            Log.err("CPU not found.");
+            return;
+        }
+
+        Log.info("Waiting for CPU to initialize...");
+
+        Time.runTask(60, () => {
+            const processor = ProcessorAccess_Companion.of(build);
+            if (processor == null) {
+                Log.err("Invalid CPU: " + build);
+                return;
+            }
+
+            processor.startServer(address, port);
+            activeProcessors.push(processor);
+        });
+    },
+
+    stopAll: () => {
+        activeProcessors.forEach((processor) => processor.stopServer());
+        Log.info(
+            "Stopped " +
+                activeProcessors.length +
+                " processor" +
+                (activeProcessors.length === 1 ? "" : "s") +
+                "."
+        );
+        activeProcessors = [];
+    },
+};
+
 Log.info("Loaded mlogv32-utils scripts.");
diff --git a/mod/src/main/kotlin/gay/object/mlogv32/Mlogv32UtilsMod.kt b/mod/src/main/kotlin/gay/object/mlogv32/Mlogv32UtilsMod.kt
@@ -95,6 +95,68 @@ class Mlogv32UtilsMod : Mod() {
 
             Log.info("Successfully dumped $bytes bytes from processor RAM to $file.")
         }
+
+        handler.register(
+            "mlogv32.start",
+            "<x> <y>",
+            "Start the processor.",
+        ) { (x, y) ->
+            val processor = getProcessor(x, y) ?: return@register
+            processor.powerSwitch.configure(true)
+            Log.info("Processor started.")
+        }
+
+        handler.register(
+            "mlogv32.pause",
+            "<x> <y>",
+            "Pause the processor.",
+        ) { (x, y) ->
+            val processor = getProcessor(x, y) ?: return@register
+            processor.singleStepSwitch.configure(true)
+            processor.pauseSwitch.configure(true)
+            Log.info("Processor paused.")
+        }
+
+        handler.register(
+            "mlogv32.step",
+            "<x> <y>",
+            "Step the processor by one instruction.",
+        ) { (x, y) ->
+            val processor = getProcessor(x, y) ?: return@register
+            processor.singleStepSwitch.configure(true)
+            processor.pauseSwitch.configure(false)
+            Log.info("Processor stepped.")
+        }
+
+        handler.register(
+            "mlogv32.unpause",
+            "<x> <y>",
+            "Unpause the processor.",
+        ) { (x, y) ->
+            val processor = getProcessor(x, y) ?: return@register
+            processor.singleStepSwitch.configure(false)
+            processor.pauseSwitch.configure(false)
+            Log.info("Processor unpaused.")
+        }
+
+        handler.register(
+            "mlogv32.stop",
+            "<x> <y>",
+            "Stop the processor.",
+        ) { (x, y) ->
+            val processor = getProcessor(x, y) ?: return@register
+            processor.powerSwitch.configure(false)
+            Log.info("Processor stopped.")
+        }
+
+        handler.register(
+            "mlogv32.status",
+            "<x> <y>",
+            "View the processor's status.",
+        ) { (x, y) ->
+            val processor = getProcessor(x, y) ?: return@register
+            Log.info(processor.getStatus().toPrettyDebugString(indentWidth = 2))
+        }
     }
 }
 
@@ -125,3 +187,20 @@ private fun getProcessor(x: String, y: String): ProcessorAccess? {
 
     return result
 }
+
+// https://gist.github.com/mayankmkh/92084bdf2b59288d3e74c3735cccbf9f?permalink_comment_id=5355537#gistcomment-5355537
+private fun Any.toPrettyDebugString(indentWidth : Int = 4) = buildString {
+    fun StringBuilder.indent(level : Int) = append("".padStart(level * indentWidth))
+    var ignoreSpace = false
+    var indentLevel = 0
+    this@toPrettyDebugString.toString().onEach {
+        when (it) {
+            '(', '[', '{' -> appendLine(it).indent(++indentLevel)
+            ')', ']', '}' -> appendLine().indent(--indentLevel).append(it)
+            ','           -> appendLine(it).indent(indentLevel).also { ignoreSpace = true }
+            ' '           -> if (ignoreSpace) ignoreSpace = false else append(it)
+            '='           -> append(" = ")
+            else          -> append(it)
+        }
+    }
+}
diff --git a/mod/src/main/kotlin/gay/object/mlogv32/ProcessorAccess.kt b/mod/src/main/kotlin/gay/object/mlogv32/ProcessorAccess.kt
@@ -118,6 +118,7 @@ class ProcessorAccess(
                                 val client = serverSocket.accept()
 
                                 if (runOnMainThread { build.isValid }) {
+                                    Log.info("Client connected!")
                                     launch {
                                         handleClient(client)
                                     }
@@ -148,11 +149,36 @@ class ProcessorAccess(
         ProcessorAccess.stopServer()
     }
 
-    fun getCSR(address: Int): UInt =
+    private fun getCSR(address: Int): UInt =
         csrs.executor.optionalVar(address + 1)
             ?.numu()
             ?: 0u
 
+    private fun getUIntVar(name: String) =
+        build.executor.optionalVar(name)?.numu() ?: 0u
+
+    fun getStatus() = StatusResponse(
+        running = powerSwitch.enabled,
+        paused = pauseSwitch.enabled,
+        state = (build.executor.optionalVar("state")?.obj() as? String) ?: "",
+        errorOutput = errorOutput.message?.toString() ?: "",
+        pc = build.executor.optionalVar("pc")?.numu(),
+        instruction = build.executor.optionalVar("instruction")?.numu(),
+        privilegeMode = build.executor.optionalVar("privilege_mode")?.numu(),
+        registers = registers.memory.take(32).map { it.toUInt() },
+        mscratch = getCSR(0x340),
+        mtvec = getCSR(0x305),
+        mepc = getCSR(0x341),
+        mcause = getCSR(0x342),
+        mtval = getCSR(0x343),
+        mstatus = getUIntVar("csr_mstatus"),
+        mip = getUIntVar("csr_mip"),
+        mie = getUIntVar("csr_mie"),
+        mcycle = (getCSR(0xB80).toULong() shl 32) or getCSR(0xB00).toULong(),
+        minstret = (getCSR(0xB82).toULong() shl 32) or getUIntVar("csr_minstret").toULong(),
+        mtime = (getUIntVar("csr_mtimeh").toULong() shl 32) or getUIntVar("csr_mtime").toULong(),
+    )
+
     private fun ramWordsSequence(startAddress: UInt) = sequence {
         require(startAddress in RAM_START..<ramEnd) { "Start address must be within RAM." }
         require(startAddress.mod(4u) == 0u) { "Start address must be aligned to 4 bytes." }
@@ -220,7 +246,6 @@ class ProcessorAccess(
 
     private suspend fun handleClient(client: Socket) {
         client.use {
-            Log.info("Client connected!")
             val rx = client.openReadChannel()
             val tx = client.openWriteChannel(true)
             while (true) {
@@ -334,9 +359,14 @@ sealed class Request {
 @SerialName("flash")
 data class FlashRequest(
     val path: String,
+    val absolute: Boolean = true,
 ) : Request() {
     override suspend fun handle(processor: ProcessorAccess, rx: ByteReadChannel, tx: ByteWriteChannel) = runOnMainThread {
-        val file = Core.files.absolute(path)
+        val file = if (absolute) {
+            Core.files.absolute(path)
+        } else {
+            Core.files.local(path)
+        }
         require(file.exists()) { "File not found." }
 
         val bytes = processor.flashRom(file)
@@ -350,9 +380,14 @@ data class DumpRequest(
     val path: String,
     val address: UInt?,
     val bytes: Int?,
+    val absolute: Boolean = true,
 ) : Request() {
     override suspend fun handle(processor: ProcessorAccess, rx: ByteReadChannel, tx: ByteWriteChannel) = runOnMainThread {
-        val file = Core.files.absolute(path)
+        val file = if (absolute) {
+            Core.files.absolute(path)
+        } else {
+            Core.files.local(path)
+        }
         file.parent().mkdirs()
 
         val address = address ?: ProcessorAccess.RAM_START
@@ -511,23 +546,7 @@ data object StopRequest : Request() {
 @SerialName("status")
 data object StatusRequest : Request() {
     override suspend fun handle(processor: ProcessorAccess, rx: ByteReadChannel, tx: ByteWriteChannel) = runOnMainThread {
-        StatusResponse(
-            running = processor.powerSwitch.enabled,
-            paused = processor.pauseSwitch.enabled,
-            errorOutput = processor.errorOutput.message?.toString() ?: "",
-            pc = processor.build.executor.optionalVar("pc")?.numu(),
-            instruction = processor.build.executor.optionalVar("instruction")?.numu(),
-            privilegeMode = processor.build.executor.optionalVar("privilege_mode")?.numu(),
-            registers = processor.registers.memory.take(32).map { it.toUInt() },
-            mscratch = processor.getCSR(0x340),
-            mtvec = processor.getCSR(0x305),
-            mepc = processor.getCSR(0x341),
-            mcause = processor.getCSR(0x342),
-            mtval = processor.getCSR(0x343),
-            mstatus = processor.build.executor.optionalVar("csr_mstatus")?.numu() ?: 0u,
-            mip = processor.build.executor.optionalVar("csr_mip")?.numu() ?: 0u,
-            mie = processor.build.executor.optionalVar("csr_mie")?.numu() ?: 0u,
-        )
+        processor.getStatus()
     }
 }
 
@@ -543,6 +562,7 @@ data class SuccessResponse(val message: String) : Response()
 data class StatusResponse(
     val running: Boolean,
     val paused: Boolean,
+    val state: String,
     val errorOutput: String,
     val pc: UInt?,
     val instruction: UInt?,
@@ -556,6 +576,9 @@ data class StatusResponse(
     val mstatus: UInt,
     val mip: UInt,
     val mie: UInt,
+    val mcycle: ULong,
+    val minstret: ULong,
+    val mtime: ULong,
 ) : Response()
 
 @Serializable
diff --git a/python/src/mlogv32/preprocessor/app.py b/python/src/mlogv32/preprocessor/app.py
@@ -97,15 +97,16 @@ def build(
     yaml_path: Path,
     cpu_config_name: Annotated[str | None, Option("-c", "--config")] = None,
     width: Annotated[int, Option("-w", "--width")] = 16,
-    height: Annotated[int, Option("-h", "--height", max=16)] = 16,
-    size: Annotated[int | None, Option("-s", "--size", max=16)] = None,
+    height: Annotated[int, Option("-h", "--height")] = 16,
+    size: Annotated[int | None, Option("-s", "--size")] = None,
     output: Annotated[Path | None, Option("-o", "--output")] = None,
     bin_path: Annotated[Path | None, Option("--bin")] = None,
     include_all: Annotated[bool, Option("--all")] = False,
     include_cpu: Annotated[bool, Option("--cpu")] = False,
     include_peripherals: Annotated[bool, Option("--peripherals")] = False,
     include_memory: Annotated[bool, Option("--memory")] = False,
     include_debugger: Annotated[bool, Option("--debugger")] = False,
+    include_keyboard: Annotated[bool, Option("--keyboard/--no-keyboard")] = True,
 ):
     """Generate a CPU schematic.
 
@@ -144,6 +145,11 @@ def build(
         width = size
         height = size
 
+    if include_keyboard and height > 16:
+        raise ValueError(
+            f"Maximum height is 16 if keyboard is enabled, but got {height}"
+        )
+
     if include_all:
         include_cpu = True
         include_peripherals = True
@@ -410,7 +416,7 @@ def add_with_label(block: Block, **labels: Unpack[Labels]):
     add_peripheral(ram_schem, 12, 17)
     add_peripheral(ram_schem, 13, 17)
     add_with_label(
-        Block(Content.SWITCH, 13, 18, True, 0),
+        Block(Content.SWITCH, 13, 18, False, 0),
         right="UART0 -> DISPLAY",
     )
 
diff --git a/python/src/mlogv32/processor_access.py b/python/src/mlogv32/processor_access.py
diff --git a/server/config/maps/empty.msav b/server/config/maps/empty.msav
