Refactor build command, remove TARGET_IPT

Author: object-Object

pyproject.toml

@@ -42,7 +42,7 @@ packages = [
 
 [tool.poe.tasks]
 build     = "python -m mlogv32.preprocessor build src/cpu/config.yaml"
-build-cpu = "python -m mlogv32.preprocessor build src/cpu/config.yaml --cpu-only"
+build-cpu = "python -m mlogv32.preprocessor build src/cpu/config.yaml --cpu"
 
 [tool.ruff]
 extend-exclude = [

python/src/mlogv32/preprocessor/app.py

@@ -2,7 +2,7 @@
 
 import re
 from pathlib import Path
-from typing import Annotated, Any, TypedDict, Unpack, cast
+from typing import Annotated, Any, TypedDict, Unpack, cast, overload
 
 import yaml
 from jinja2 import Environment, FileSystemLoader, StrictUndefined
@@ -78,20 +78,44 @@ def configs(yaml_path: Path):
 @app.command()
 def build(
     yaml_path: Path,
+    cpu_config_name: Annotated[str | None, Option("-c", "--config")] = None,
     width: Annotated[int, Option("-w", "--width")] = 16,
     height: Annotated[int, Option("-h", "--height")] = 16,
     size: Annotated[int | None, Option("-s", "--size")] = None,
     output: Annotated[Path | None, Option("-o", "--output")] = None,
-    cpu_only: bool = False,
+    include_all: Annotated[bool, Option("--all")] = False,
+    include_cpu: Annotated[bool, Option("--cpu")] = False,
+    include_peripherals: Annotated[bool, Option("--peripherals")] = False,
 ):
     """Generate a CPU schematic."""
 
     if size:
         width = size
         height = size
 
+    if include_all or not (include_cpu or include_peripherals):
+        include_cpu = True
+        include_peripherals = True
+
     config = BuildConfig.load(yaml_path)
 
+    if cpu_config_name:
+        with config.configs.open("rb") as f:
+            cpu_configs: ConfigsYaml = yaml.load(f, yaml.Loader)
+
+        if cpu_config_name not in cpu_configs["configs"]:
+            raise KeyError(f"Unknown config name: {cpu_config_name}")
+
+        configs(config.configs)
+
+        config_code = (
+            (config.configs.parent / cpu_config_name)
+            .with_suffix(".mlog")
+            .read_text("utf-8")
+        )
+    else:
+        config_code = ""
+
     worker_output = get_template_output_path(config.templates.worker)
     worker_code = render_template(
         config.templates.worker,
@@ -125,59 +149,103 @@ def build(
 
     schem = Schematic()
 
+    @overload
+    def add_peripheral(block: Block) -> None: ...
+
+    @overload
+    def add_peripheral(block: Schematic, x: int, y: int) -> None: ...
+
+    def add_peripheral(block: Block | Schematic, x: int = 0, y: int = 0):
+        if not include_peripherals:
+            return
+        match block:
+            case Block():
+                schem.add_block(block)
+            case Schematic():
+                schem.add_schem(block, x, y)
+
+    def add_cpu(block: Block):
+        if include_cpu:
+            schem.add_block(block)
+
+    def add_label(x: int, y: int, **labels: Unpack[Labels]):
+        label = "\n".join(
+            template.format(label)
+            for key, template in [
+                ("up", "{} ⇧"),
+                ("left", "⇦ {}"),
+                ("right", "{} ⇨"),
+                ("down", "{} ⇩"),
+            ]
+            if (label := labels.get(key))
+        )
+        add_peripheral(
+            Block(
+                block=Content.MESSAGE,
+                x=x,
+                y=y,
+                config=label,
+                rotation=0,
+            )
+        )
+
+    def add_with_label(block: Block, **labels: Unpack[Labels]):
+        add_label(block.x - 1, block.y, **labels)
+        add_peripheral(block)
+
+    # peripherals
+
     for x in lenrange(0, 16):
         for y in lenrange(0, 16):
-            schem.add_block(simple_block(BEContent.TILE_LOGIC_DISPLAY, x, y))
+            add_peripheral(simple_block(BEContent.TILE_LOGIC_DISPLAY, x, y))
 
     display_link = ProcessorLink(0, 0, "")
 
-    schem.add_schem(lookups_schem, 0, 16)
+    add_peripheral(lookups_schem, 0, 16)
     lookup_links = [ProcessorLink(x=i % 4, y=16 + i // 4, name="") for i in range(16)]
 
-    add_label(schem, 4, 19, right="UART0, UART2", down="LABELS")
-    schem.add_block(simple_block(Content.WORLD_CELL, 4, 18))
-    schem.add_block(simple_block(Content.WORLD_CELL, 4, 17))
-    add_label(schem, 4, 16, up="COSTS", right="UART1, UART3")
+    add_label(4, 19, right="UART0, UART2", down="LABELS")
+    add_peripheral(simple_block(Content.WORLD_CELL, 4, 18))
+    add_peripheral(simple_block(Content.WORLD_CELL, 4, 17))
+    add_label(4, 16, up="COSTS", right="UART1, UART3")
 
     labels_link = ProcessorLink(4, 18, "")
     costs_link = ProcessorLink(4, 17, "")
 
     uart_links = list[ProcessorLink]()
     for x in lenrange(5, 4, 2):
         for y in lenrange(18, -4, -2):
-            schem.add_block(simple_block(Content.MEMORY_BANK, x, y))
+            add_peripheral(simple_block(Content.MEMORY_BANK, x, y))
             uart_links.append(ProcessorLink(x, y, ""))
 
-    schem.add_block(simple_block(Content.MEMORY_CELL, 9, 19))
-    schem.add_schem(ram_schem, 9, 18)
-    schem.add_schem(ram_schem, 9, 17)
-    schem.add_block(Block(Content.MICRO_PROCESSOR, 9, 16, ProcessorConfig("", []), 0))
+    add_peripheral(simple_block(Content.MEMORY_CELL, 9, 19))
+    add_peripheral(ram_schem, 9, 18)
+    add_peripheral(ram_schem, 9, 17)
+    add_peripheral(
+        Block(Content.MICRO_PROCESSOR, 9, 16, ProcessorConfig(config_code, []), 0)
+    )
 
     registers_link = ProcessorLink(9, 19, "")
     csrs_link = ProcessorLink(9, 18, "")
     incr_link = ProcessorLink(9, 17, "")
     config_link = ProcessorLink(9, 16, "")
 
     add_with_label(
-        schem,
         simple_block(Content.MESSAGE, 11, 19),
         left="REGISTERS",
         right="ERROR_OUTPUT",
     )
     add_with_label(
-        schem,
         Block(Content.SWITCH, 11, 18, False, 0),
         left="CSRS",
         right="POWER_SWITCH",
     )
     add_with_label(
-        schem,
         Block(Content.SWITCH, 11, 17, False, 0),
         left="INCR",
         right="PAUSE_SWITCH",
     )
     add_with_label(
-        schem,
         Block(Content.SWITCH, 11, 16, False, 0),
         left="CONFIG",
         right="SINGLE_STEP_SWITCH",
@@ -188,11 +256,9 @@ def build(
     pause_switch_link = ProcessorLink(11, 17, "")
     single_step_switch_link = ProcessorLink(11, 16, "")
 
-    # hack
-    if cpu_only:
-        schem = Schematic()
+    # CPU
 
-    schem.add_block(
+    add_cpu(
         Block(
             block=Content.WORLD_PROCESSOR,
             x=16,
@@ -229,7 +295,7 @@ def build(
             if x == 16 and y == 0:
                 continue
 
-            schem.add_block(
+            add_cpu(
                 Block(
                     block=Content.WORLD_PROCESSOR,
                     x=x,
@@ -282,33 +348,6 @@ class Labels(TypedDict, total=False):
     down: str
 
 
-def add_label(schem: Schematic, x: int, y: int, **labels: Unpack[Labels]):
-    label = "\n".join(
-        template.format(label)
-        for key, template in [
-            ("up", "{} ⇧"),
-            ("left", "⇦ {}"),
-            ("right", "{} ⇨"),
-            ("down", "{} ⇩"),
-        ]
-        if (label := labels.get(key))
-    )
-    schem.add_block(
-        Block(
-            block=Content.MESSAGE,
-            x=x,
-            y=y,
-            config=label,
-            rotation=0,
-        )
-    )
-
-
-def add_with_label(schem: Schematic, block: Block, **labels: Unpack[Labels]):
-    add_label(schem, block.x - 1, block.y, **labels)
-    schem.add_block(block)
-
-
 def create_jinja_env(template_dir: Path):
     env = Environment(
         loader=FileSystemLoader(template_dir),

python/src/mlogv32/preprocessor/models.py

@@ -28,6 +28,7 @@ def _RelativePath_after(path: Path):
 class BuildConfig(BaseModel):
     templates: Templates
     schematics: Schematics
+    configs: RelativePath
     inputs: dict[str, Any]
     instructions: list[Instruction]
 

src/config/base.mlog.jinja

@@ -1,7 +1,6 @@
     # per-world config options for mlogv32
 
     # reloaded after unpausing
-    set TARGET_IPT {{#TARGET_IPT}}
     set BREAKPOINT_ADDRESS {{#BREAKPOINT_ADDRESS}}
 
     # loaded at reset only
@@ -29,14 +28,13 @@
 #%- if false
 # {% raw %}
 set {{ null
-set TARGET_IPT TARGET_IPT
-set BREAKPOINT_ADDRESS BREAKPOINT_ADDRESS
-set MEMORY_WIDTH MEMORY_WIDTH
-set ROM_SIZE ROM_SIZE
-set RAM_SIZE RAM_SIZE
-set ICACHE_SIZE ICACHE_SIZE
-set UART_FIFO_MODULO UART_FIFO_MODULO
-set MEMORY_X MEMORY_X
-set MEMORY_Y MEMORY_Y
+set _ BREAKPOINT_ADDRESS
+set _ MEMORY_WIDTH
+set _ ROM_SIZE
+set _ RAM_SIZE
+set _ ICACHE_SIZE
+set _ UART_FIFO_MODULO
+set _ MEMORY_X
+set _ MEMORY_Y
 # {% endraw %}
 #% endif

src/config/configs.yaml

@@ -1,7 +1,6 @@
 template: base.mlog.jinja
 
 defaults:
-  TARGET_IPT: 500000
   BREAKPOINT_ADDRESS: '0x'
   UART_FIFO_CAPACITY: 253
 
@@ -15,7 +14,6 @@ configs:
     ICACHE_ROWS: 6
 
   micro:
-    TARGET_IPT: 250000 # we're running two of these at once, so underclock it
     MEMORY_X_OFFSET: -9
     MEMORY_Y_OFFSET: -32
     MEMORY_WIDTH: 16

src/cpu/config.yaml

@@ -6,6 +6,8 @@ schematics:
   lookups: ../../schematics/lookup_procs.msch
   ram: ../../schematics/ram_proc.msch
 
+configs: ../config/configs.yaml
+
 inputs:
   # 18 (main__read_icache) + 8 (end)
   base_instruction_cost: 26