Start working on running privileged tests, set mtvec to 0xfffffffc on reset and halt if reached, add instruction breakpoint, load test .text into RAM

Author: object-Object

README.md

@@ -22,14 +22,17 @@ The main CPU code is generated from `src/main.mlog.jinja` using a custom Jinja-b
 | `0x80000000` | RAM   |
 | `0xf0000000` | MMIO  |
 
-Addresses `0xf0000000` - `0xffffffff` are reserved for MMIO.
-
-| Address      | Value       |
-| ------------ | ----------- |
-| `0xf0000000` | `mtime`     |
-| `0xf0000004` | `mtimeh`    |
-| `0xf0000008` | `mtimecmp`  |
-| `0xf000000c` | `mtimecmph` |
+Addresses `0xf0000000` - `0xffffffff` are reserved for MMIO and other system purposes.
+
+| Address      | Value                 |
+| ------------ | --------------------- |
+| `0xf0000000` | `mtime`               |
+| `0xf0000004` | `mtimeh`              |
+| `0xf0000008` | `mtimecmp`            |
+| `0xf000000c` | `mtimecmph`           |
+| `0xfffffffc` | `mtvec` default value |
+
+The machine trap vector CSR `mtvec` is initialized to `0xfffffffc` at reset. To help catch issues with uninitialized `mtvec`, the processor will halt if code jumps to this address.
 
 ## ISA
 

riscof/mlogv32/env/link.ld

@@ -2,39 +2,45 @@ OUTPUT_ARCH( "riscv" )
 ENTRY(rvtest_entry_point)
 
 MEMORY {
-    ROM  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x200000
-    RAM  (rwx) : ORIGIN = 0x80000000, LENGTH = 0x200000
+    ROM  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x480000
+    RAM  (rwx) : ORIGIN = 0x80000000, LENGTH = 0x480000
     MMIO (rw)  : ORIGIN = 0xf0000000, LENGTH = 16
 }
 
 SECTIONS
 {
-    .text : {
-        KEEP(*(.text.init));
-        *(.text)
+    .text.init.rom : ALIGN(4) {
+        KEEP(*(.text.init.rom));
         . = ALIGN(4);
-        __etext = .;
+        __etext_rom = .;
     } > ROM
 
+    .text : ALIGN(4) {
+        __stext = .;
+        *(.text.init);
+        *(.text);
+        . = ALIGN(4);
+        __etext = .;
+    } > RAM AT > ROM
+
+    __sitext = LOADADDR(.text);
+
     .data : ALIGN(4) {
         __sdata = .;
         *(.data);
         *(.data.string);
+        . = ALIGN(4);
+        __edata = .;
     } > RAM AT > ROM
 
-    . = ALIGN(4);
-    __edata = .;
-
     __sidata = LOADADDR(.data);
 
     .bss (NOLOAD) : ALIGN(4) {
-        . = ALIGN(4);
         __sbss = .;
         *(.bss);
+        . = ALIGN(4);
+        __ebss = .;
     } > RAM
 
-    . = ALIGN(4);
-    __ebss = .;
-
     _end = .;
 }

riscof/mlogv32/env/model_test.h

@@ -10,11 +10,27 @@
 #define RVMODEL_HALT                                              \
   .insn i CUSTOM_0, 0, zero, zero, 0;
 
-// initialize icache, .data, and .bss
+// initialize icache, .text, .data, and .bss
+// see https://github.com/riscv-non-isa/riscv-arch-test/issues/202
 #define RVMODEL_BOOT \
   .option norelax; \
-  la t0, __etext; \
+  .section .text.init.rom; \
+  \
+  la t0, __etext_rom; \
   .insn i CUSTOM_0, 0, zero, t0, 5; \
+  \
+  la t0, __sitext; \
+  la t1, __stext; \
+  la t2, __etext; \
+mlogv32_load_text: \
+  bgeu t1, t2, mlogv32_text_done; \
+  lb t3, 0(t0); \
+  sb t3, 0(t1); \
+  addi t0, t0, 1; \
+  addi t1, t1, 1; \
+  j mlogv32_load_text; \
+mlogv32_text_done: \
+  \
   la t0, __sidata; \
   la t1, __sdata; \
   la t2, __edata; \
@@ -26,14 +42,17 @@ mlogv32_load_data: \
   addi t1, t1, 1; \
   j mlogv32_load_data; \
 mlogv32_data_done: \
+  \
   la t0, __sbss; \
   la t1, __ebss; \
 mlogv32_clear_bss: \
   bgeu t0, t1, mlogv32_bss_done; \
   sb zero, 0(t0); \
   addi t0, t0, 1; \
   j mlogv32_clear_bss; \
-mlogv32_bss_done:
+mlogv32_bss_done: \
+  \
+  tail rvtest_init;
 
 //RV_COMPLIANCE_DATA_BEGIN
 #define RVMODEL_DATA_BEGIN                                              \

riscof/mlogv32/mlogv32_isa.yaml

@@ -1,8 +1,43 @@
 # https://riscv-config.readthedocs.io/en/stable/yaml-specs.html
 hart_ids: [0]
 hart0:
-  ISA: RV32IMA
+  ISA: RV32IMAUZicsr_Zifencei
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
+  Privilege_Spec_Version: '1.11'
+  hw_data_misaligned_support: false
+  pmp_granularity: 0
   supported_xlen: [32]
- 
+  mtval_update: 0
+  misa:
+    # X bit is disabled because riscv-config doesn't seem to like it
+    # 0b01000000000100000001000100000001
+    reset-val: 0x40101101
+    rv32:
+      accessible: true
+      extensions:
+        implemented: true
+        type:
+          warl:
+            legal:
+              - extensions[25:0] in [0x0101101]
+            wr_illegal:
+              - unchanged
+  cycle:
+    rv32:
+      accessible: true
+  cycleh:
+    rv32:
+      accessible: true
+  time:
+    rv32:
+      accessible: true
+  timeh:
+    rv32:
+      accessible: true
+  instret:
+    rv32:
+      accessible: true
+  instreth:
+    rv32:
+      accessible: true

riscof/mlogv32/mlogv32_platform.yaml

@@ -2,3 +2,9 @@ reset:
   address: 0x0
 nmi:
   label: nmi_vector # we don't have an nmi vector, but riscof gets mad if this is removed
+mtime:
+  implemented: true
+  address: 0xf0000000
+mtimecmp:
+  implemented: true
+  address: 0xf0000008

riscof/mlogv32/riscof_mlogv32.py

@@ -184,15 +184,15 @@ def runTests(self, testlist: dict[str, Any]):
 
                 logger.debug(f"Compile command: {compile_cmd}")
                 if utils.shellCommand(compile_cmd).run(cwd=test_dir) != 0:
-                    raise RuntimeError("Compile failed!")
+                    raise RuntimeError(f"Compile failed: {testname}")
 
                 logger.debug(f"Objcopy command: {objcopy_cmd}")
                 if utils.shellCommand(objcopy_cmd).run(cwd=test_dir) != 0:
-                    raise RuntimeError("Objcopy failed!")
+                    raise RuntimeError(f"Objcopy failed: {testname}")
 
-                # logger.debug(f"Objdump command: {objdump_cmd}")
-                # if utils.shellCommand(objdump_cmd).run(cwd=test_dir) != 0:
-                #     raise RuntimeError("Objdump failed!")
+                logger.debug(f"Objdump command: {objdump_cmd}")
+                if utils.shellCommand(objdump_cmd).run(cwd=test_dir) != 0:
+                    raise RuntimeError(f"Objdump failed: {testname}")
 
                 if not self.target_run:
                     continue
@@ -229,8 +229,8 @@ def runTests(self, testlist: dict[str, Any]):
                         sig.write(word.hex() + "\n")
 
                 if msg := processor.status().error_output:
-                    logger.error(f"Processor execution failed: {msg}")
-                    # raise RuntimeError(f"Processor execution failed: {msg}")
+                    # logger.error(f"Processor execution failed: {msg}")
+                    raise RuntimeError(f"Processor execution failed: {msg}")
 
                 logger.debug(f"Finished test: {testname}")
 

riscof/riscv-arch-test

@@ -1,6 +1,6 @@
     # per-world config options
-    set TARGET_IPT 500000
 
+    # loaded at reset only
     set MEMORY_X_OFFSET -11  # x offset from this proc to bottom left memory proc
     set MEMORY_Y_OFFSET -26  # y offset from this proc to bottom left memory proc
     set MEMORY_WIDTH 32  # physical width of the memory procs
@@ -9,6 +9,10 @@
     set RAM_SIZE    0x200000  # RAM size in bytes (rwx)
     set ICACHE_SIZE 0x200000  # icache size in variables, or bytes of memory it can represent; 4x less dense than ROM/RAM
 
+    # reloaded after unpausing
+    set TARGET_IPT 500000
+    set BREAKPOINT_ADDRESS null
+
     # computed values
     op add MEMORY_X @thisx MEMORY_X_OFFSET
     op add MEMORY_Y @thisy MEMORY_Y_OFFSET

src/config.mlog

@@ -200,6 +200,11 @@ loop:
     op add ret @counter 1
     jump mark_memory always
 
+    setmarker remove mark_memory_id
+    op add tmp mark_memory_id 1
+    setmarker remove tmp
+    jump loop__no_mark_icache lessThanEq ICACHE_SIZE 0
+
     print "ICACHE_START\n{0}"
     set address ICACHE_START
     op add ret @counter 1
@@ -209,6 +214,7 @@ loop:
     op sub address ICACHE_END 1
     op add ret @counter 1
     jump mark_memory always
+loop__no_mark_icache:
 
     # clear
 
@@ -356,11 +362,13 @@ loop:
     op add ret @counter 1
     jump format_bin always
 
-    print "mie      = {0}\n\n"
+    print "mie      = {0}\n"
     set n mie
     op add ret @counter 1
     jump format_bin always
 
+    #{{'\n'}} {{ print(0, 17) }}
+
     print "cycle   = {0}\n"
     format cycle
 
@@ -370,7 +378,7 @@ loop:
     print "instret = {0}\n\n"
     format instret
 
-    #{{'\n'}} {{ print(0, 17) }}
+    #{{'\n'}} {{ print(0, 33) }}
 
     # column 2
 

src/debugger.mlog.jinja

@@ -63,7 +63,6 @@ loop:
     write 0 CSRS "{{ 'mimpid'|csr }}"
 
     # default values for writable CSRs
-    write 0 CSRS "{{ 'mtvec'|csr }}"
     write 0 CSRS "{{ 'mepc'|csr }}"
     write 0 CSRS "{{ 'mscratch'|csr }}"
     write 0 CSRS "{{ 'mie'|csr }}"