Start working on implementing M-mode and U-mode

Author: object-Object

.gitignore

@@ -5,6 +5,8 @@
 *.hex
 /build/
 /out/
+
+/src/init.mlog
 /src/main.mlog
 
 node_modules/

.vscode/settings.json

@@ -25,5 +25,6 @@
     "ruff.organizeImports": true,
     "ruff.lint.ignore": ["I"],
     "python.languageServer": "Pylance",
-    "python.analysis.diagnosticMode": "workspace"
+    "python.analysis.diagnosticMode": "workspace",
+    "python.analysis.packageIndexDepths": [{ "name": "jinja2", "depth": 2 }]
 }

README.md

@@ -12,12 +12,26 @@ Code begins executing at address `0x4`. Address `0x0` must contain the size of t
 
 The main CPU code is generated from `src/main.mlog.jinja` using a custom Jinja-based preprocessor (`python/src/mlogv32/preprocessor`).
 
-## Extensions
+### MMIO
+
+Addresses `0xf0000000` - `0xffffffff` are reserved for MMIO.
+
+| Address      | Value       |
+| ------------ | ----------- |
+| `0xf0000000` | `mtime`     |
+| `0xf0000004` | `mtimeh`    |
+| `0xf0000008` | `mtimecmp`  |
+| `0xf000000c` | `mtimecmph` |
+
+## ISA
 
 `RV32IMAZicntr_Zicsr_Zifencei_Zihintpause`
 
+Supported privilege levels: M, U
+
 | Extension   | Version |
 | ----------- | ------- |
+| M-mode      | 1.13    |
 | I           | 2.1     |
 | M           | 2.0     |
 | A           | 2.1     |

nodemon.json

@@ -1,5 +1,5 @@
 {
     "watch": ["src", "python"],
     "ext": "jinja,py",
-    "exec": "python -m mlogv32.preprocessor src/main.mlog.jinja -o src/main.mlog"
+    "exec": "python -m mlogv32.preprocessor src/main.mlog.jinja -o src/main.mlog && python -m mlogv32.preprocessor src/init.mlog.jinja -o src/init.mlog"
 }

python/src/mlogv32/preprocessor/app.py

@@ -4,9 +4,13 @@
 from jinja2 import Environment, FileSystemLoader, StrictUndefined
 from typer import Option, Typer
 
+from mlogv32.preprocessor.extensions import CommentStatement
+
 from . import filters
 
-app = Typer()
+app = Typer(
+    pretty_exceptions_show_locals=False,
+)
 
 
 @app.command()
@@ -24,6 +28,9 @@ def main(
         lstrip_blocks=True,
         trim_blocks=True,
         undefined=StrictUndefined,
+        extensions=[
+            CommentStatement,
+        ],
     )
     env.filters |= {  # pyright: ignore[reportAttributeAccessIssue]
         "ram_variable": filters.ram_variable,

python/src/mlogv32/preprocessor/extensions.py

@@ -0,0 +1,20 @@
+from jinja2.ext import Extension
+
+
+class CommentStatement(Extension):
+    """Allows writing inline expressions without causing an mlogls error.
+
+    For example:
+    ```
+    op add foo bar {{# 1 }}
+    ```
+    """
+
+    def preprocess(
+        self,
+        source: str,
+        name: str | None,
+        filename: str | None = None,
+    ) -> str:
+        # hacky
+        return source.replace("{{#", "{{")

python/src/mlogv32/preprocessor/filters.py

@@ -55,25 +55,6 @@ def quote(value: Any):
     "timeh": 0xC81,
     "instreth": 0xC82,
     **{f"hpmcounter{i}h": 0xC80 + i for i in range(3, 32)},
-    # supervisor
-    "sstatus": 0x100,
-    "sie": 0x104,
-    "stvec": 0x105,
-    "scounteren": 0x106,
-    "senvcfg": 0x10A,
-    "scountinhibit": 0x120,
-    "sscratch": 0x140,
-    "sepc": 0x141,
-    "scause": 0x142,
-    "stval": 0x143,
-    "sip": 0x144,
-    "scountovf": 0xDA0,
-    "satp": 0x180,
-    "scontext": 0x5A8,
-    "sstateen0": 0x10C,
-    "sstateen1": 0x10D,
-    "sstateen2": 0x10E,
-    "sstateen3": 0x10F,
     # machine
     "mvendorid": 0xF11,
     "marchid": 0xF12,
@@ -110,4 +91,17 @@ def quote(value: Any):
     "mstateen1h": 0x31D,
     "mstateen2h": 0x31E,
     "mstateen3h": 0x31F,
+    "mnscratch": 0x740,
+    "mnepc": 0x741,
+    "mncause": 0x742,
+    "mnstatus": 0x744,
+    "mcycle": 0xB00,
+    "minstret": 0xB02,
+    **{f"mhpmcounter{i}": 0xB00 + i for i in range(3, 32)},
+    "mcycleh": 0xB80,
+    "minstreth": 0xB82,
+    **{f"mhpmcounter{i}h": 0xB80 + i for i in range(3, 32)},
+    "mcountinhibit": 0x320,
+    **{f"mhpmevent{i}": 0x320 + i for i in range(3, 32)},
+    **{f"mhpmevent{i}h": 0x720 + i for i in range(3, 32)},
 }

src/init_incr_proc.mlog src/init.mlog.jinjasrc/init_incr_proc.mlog renamed to src/init.mlog.jinja

@@ -1,19 +1,21 @@
-# this processor initializes INCR using a lookup table
-# the lookup table must be linked first, and INCR must be linked last
+# this processor initializes INCR using a lookup table, and sets readonly CSR values
+# the lookup table must be linked first
 
     set LOOKUP_START 0
-    set LOOKUP_LINKS 16
+    set EXPECTED_LINKS 17
     set LOOKUP_PROC_SIZE 260
     set RAM_PROC_SIZE 4096
 
     # wait until ready
 reset:
-    jump reset lessThanEq @links LOOKUP_LINKS # 16 lookup procs + 1 incr proc
-    op sub i @links 1
-    getlink INCR i
+    jump reset lessThan @links EXPECTED_LINKS
+    
+    set INCR processor17
     read type INCR "_type"
     jump reset equal type "lookup" # sanity check
 
+    set CSRS processor18
+
     op div wait LOOKUP_PROC_SIZE 120 # micro proc instructions/sec
     op ceil wait wait
     wait wait
@@ -38,6 +40,28 @@ loop:
     op add address address 1
     jump loop lessThanEq address RAM_PROC_SIZE
 
+    # initialize CSRS
+
+    # misa
+    # XLEN=32    --
+    # 0            ----
+    # IMAX             ZYXWVUTSRQPONMLKJIHGFEDCBA
+    write 0b01000000100000000001000100000001 CSRS "{{ 'misa'|csr }}"
+
+    # mstatush
+    # WPRI  --------------------------  ----
+    # MBE                             -
+    # SBE                              -
+    write 0b00000000000000000000000000000000 CSRS "{{ 'mstatush'|csr }}"
+
+    # mlogv32 only has one hart, so mhartid is required to be zero
+    write 0 CSRS "{{ 'mhartid'|csr }}"
+
+    # unimplemented fields
+    write 0 CSRS "{{ 'mvendorid'|csr }}"
+    write 0 CSRS "{{ 'marchid'|csr }}"
+    write 0 CSRS "{{ 'mimpid'|csr }}"
+
     stop
 
 # given a value 0 <= address < RAM_PROC_SIZE, resolve that variable in the lookup table

src/macros/bits.jinja

@@ -0,0 +1,25 @@
+#%# usage: op or value value {{# set_bits(high, low) }}
+{% macro set_bits(high, low=none) -%}
+  {%- if low == none -%}
+    {%- set low = high -%}
+  {%- elif high < low -%}
+    {%- set high, low = low, high -%}
+  {%- endif -%}
+  0b
+  {{- '0' * (31 - high) -}}
+  {{- '1' * (high - low + 1) -}}
+  {{- '0' * low -}}
+{%- endmacro %}
+
+#%# usage: op and value value {{# clear_bits(high, low) }}
+{% macro clear_bits(high, low=none) -%}
+  {%- if low == none -%}
+    {%- set low = high -%}
+  {%- elif high < low -%}
+    {%- set high, low = low, high -%}
+  {%- endif -%}
+  0b
+  {{- '1' * (31 - high) -}}
+  {{- '0' * (high - low + 1) -}}
+  {{- '1' * low -}}
+{%- endmacro %}

src/main.constants.jinja

@@ -14,4 +14,6 @@
 {% set KBCONV_DATA = 'cell2' %}
 {% set DISPLAY = 'display1' %}
 
+{% set MMIO_START = '0xf0000000' %}
+
 {% block contents %}{% endblock %}