Fix linux poweroff syscon

Author: object-Object

README.md

@@ -33,7 +33,7 @@ The CPU is implemented using a variable-size build-order-independent subframe ar
 | `0xf0000030` | `0x20`       | R/W         | UART1       |
 | `0xf0000050` | `0x20`       | R/W         | UART2       |
 | `0xf0000070` | `0x20`       | R/W         | UART3       |
-| `0xfffffff0` | `0x4`        | W           | Syscon      |
+| `0xfffffff0` | `0x4`        | R/W         | Syscon      |
 
 \* Atomic instructions are only supported in RAM.
 
@@ -88,14 +88,15 @@ Note that the processor itself does not set the TX overflow flag or prevent code
 
 ### Syscon
 
-Address `0xfffffff0` contains a simple write-only peripheral which can be used to control the system by writing values from the following table. Unsupported values will have no effect if written.
+Address `0xfffffff0` contains a simple memory-mapped peripheral which can be used to control the system by writing values from the following table. Unsupported values will have no effect if written. Reads will always return `0`.
 
 | Value        | Effect    |
 | ------------ | --------- |
 | `0x00000000` | Power off |
 | `0x00000001` | Reboot    |
+| `0x00000002` | Power off |
 
-Additionally, the machine trap vector CSR `mtvec` is initialized to `0xfffffff0` at reset. To help catch issues with uninitialized `mtvec`, the processor will halt and output an error message if code jumps to this address.
+Additionally, the trap vector CSRs `mtvec` and `stvec` are initialized to `0xfffffff0` at reset. To help catch issues with uninitialized trap vectors, the processor will halt and output an error message if a trap jumps to this address.
 
 ## ISA
 

linux/buildroot/board/mlogv32/dts/mlogv32.dtb

@@ -96,7 +96,7 @@
             compatible = "syscon-poweroff";
             regmap = <&syscon>;
             offset = <0x0>;
-            value = <0x0>;
+            value = <0x2>;
         };
 
         reboot {

linux/buildroot/board/mlogv32/dts/mlogv32.dts

@@ -961,6 +961,10 @@ load_rom_word_unchecked:
 # address, mcause, mtval -> result
 load_mmio_word:
 #% do declare_locals(access_uart_locals)
+    # linux syscon driver does a read-modify-write, so the syscon needs to be readable
+    set result 0
+    jump load_mmio_word__ret equal address {{SYSCON}}
+
     # the extra 3 at the start is in case we jump here from address translation
     # in that case, address may be up to 34 bits
     op sub $$offset address {{MMIO_START}}
@@ -977,9 +981,9 @@ load_mmio_word:
 #directive end_assert_length
 
     # MCR, MSR, and SPR are all hardwired to zero
-    set result 0
     jump load_mmio_word__uart_lsr equal $$offset 0x24
     jump load_mmio_word__not_zero lessThan $$offset 0x20
+load_mmio_word__ret:
     set @counter ret
 load_mmio_word__not_zero:
 
@@ -1772,9 +1776,9 @@ store_mmio_word_unchecked__uart_fcr__no_reset_tx:
     jump end_instruction always
 
 store_value__syscon:
-    jump state->halt equal rs2 0
+    jump end_instruction greaterThan rs2 2
     jump state->reset equal rs2 1
-    jump end_instruction always
+    jump state->halt always # 0 or 2 (for linux syscon)
 
 LR.W:
     # R-type: rs1, rs2=0, rd_id