Fix old variable references in controller

Author: object-Object

src/cpu/controller.mlog.jinja

@@ -207,7 +207,7 @@ end_slow_init:
 
     # clear delegated traps
     write 0 {{CSRS}} "{{ 'medeleg'|csr }}"
-    set csr_mideleg 0
+    write 0 {{CSRS}} "{{ 'mideleg'|csr }}"
 
     # clear pending/enabled interrupts
     set csr_mip 0
@@ -218,7 +218,7 @@ end_slow_init:
     write {{SYSCON}} {{CSRS}} "{{ 'stvec'|csr }}"
 
     # clear satp
-    set csr_satp 0
+    write 0 {{CSRS}} "{{ 'satp'|csr }}"
 
     # misa
     # XLEN=32 --
@@ -417,7 +417,5 @@ set _ csr_minstret
 set _ csr_mstatus
 set _ csr_mip
 set _ csr_mie
-set _ csr_satp
-set _ csr_mideleg
 # {% endraw %}
 #% endif