Move mcycle out of CSRS

Author: object-Object

mod/src/main/kotlin/gay/object/mlogv32/ProcessorAccess.kt

@@ -174,7 +174,7 @@ class ProcessorAccess(
         mstatus = getUIntVar("csr_mstatus"),
         mip = getUIntVar("csr_mip"),
         mie = getUIntVar("csr_mie"),
-        mcycle = (getCSR(0xB80).toULong() shl 32) or getCSR(0xB00).toULong(),
+        mcycle = (getCSR(0xB80).toULong() shl 32) or getUIntVar("csr_mcycle").toULong(),
         minstret = (getCSR(0xB82).toULong() shl 32) or getUIntVar("csr_minstret").toULong(),
         mtime = (getUIntVar("csr_mtimeh").toULong() shl 32) or getUIntVar("csr_mtime").toULong(),
     )

src/cpu/controller.mlog.jinja

@@ -202,7 +202,7 @@ end_slow_init:
     set csr_stimecmph 0
     set csr_minstret 0
     write 0 {{CSRS}} "{{ 'minstreth'|csr }}"
-    write 0 {{CSRS}} "{{ 'mcycle'|csr }}"
+    set csr_mcycle 0
     write 0 {{CSRS}} "{{ 'mcycleh'|csr }}"
 
     # clear delegated traps
@@ -407,6 +407,7 @@ set _ __etext
 set _ privilege_mode
 set _ effective_privilege_mode
 set _ reservation_set
+set _ csr_mcycle
 set _ csr_mtime
 set _ csr_mtimeh
 set _ csr_mtimecmp

src/cpu/cpu.yaml

@@ -169,7 +169,7 @@ csrs:
 
   # counter/timers
   cycle:
-    read: LABEL
+    read: mcycle
   time:
     read: LABEL
   instret:
@@ -345,8 +345,8 @@ csrs:
 
   # counter/timers
   mcycle:
-    read: csrs
-    write: csrs
+    read: LABEL
+    write: LABEL
   minstret:
     read: LABEL
     write: LABEL

src/cpu/worker.mlog.jinja

@@ -27,7 +27,7 @@
 
 #% set labels.next_tick = 14
 
-#% set labels.end_instruction_with_rd_and_poll_interrupts = 152
+#% set labels.end_instruction_with_rd_and_poll_interrupts = 151
 #% set labels.end_instruction_with_rd_and_fire_interrupts = _labels_vals|last + 1
 #% set labels.end_instruction_with_rd                     = _labels_vals|last + 1
 #% set labels.end_instruction                             = _labels_vals|last + 2
@@ -86,6 +86,7 @@ reset:
     read _address prev_proc "_address"
     read address prev_proc "address"
     read breakpoint_address prev_proc "breakpoint_address"
+    read csr_mcycle prev_proc "csr_mcycle"
     read csr_mie prev_proc "csr_mie"
     read csr_minstret prev_proc "csr_minstret"
     read csr_mip prev_proc "csr_mip"
@@ -136,22 +137,19 @@ reset:
 
     # these variables don't need to be saved because this should only ever run at the start of a tick
 
-#directive push_saved __mcycle __mcycleh
     # increment mcycle
-    read __mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
-    op add __mcycle __mcycle 1
-    jump reset__no_overflow lessThan __mcycle 0x100000000
+    op add csr_mcycle csr_mcycle 1
+    jump reset__no_overflow lessThan csr_mcycle 0x100000000
 
     # overflow mcycle into mcycleh
     # TODO: handle mcycleh overflow
-    set __mcycle 0
+    set csr_mcycle 0
+#directive push_saved __mcycleh
     read __mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
     op add __mcycleh __mcycleh 1
     write __mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
-
+#directive pop_saved __mcycleh
 reset__no_overflow:
-    write __mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
-#directive pop_saved __mcycle __mcycleh
 
     # if we just started executing, don't restore @counter
     jump poll_interrupts equal prev_proc {{CONTROLLER}}
@@ -2569,11 +2567,15 @@ csr_write_stimecmph:
     set csr_stimecmph result
     jump end_instruction_with_rd_and_poll_interrupts always
 
-csr_read_cycle:
+csr_read_mcycle:
 #% do declare_locals(modify_csr_locals)
-    read rd {{CSRS}} "{{ 'mcycle'|csr }}"
+    set rd csr_mcycle
     jump check_xcounteren always
 
+csr_write_mcycle:
+    set csr_mcycle result
+    jump end_instruction_with_rd always
+
 csr_read_cycleh:
 #% do declare_locals(modify_csr_locals)
     read rd {{CSRS}} "{{ 'mcycleh'|csr }}"
@@ -2787,7 +2789,7 @@ jump decode_JALR always
 jump decode_JAL always
 jump decode_SYSTEM always
 jump csr_read_csrs always
-jump csr_read_cycle always
+jump csr_read_mcycle always
 jump csr_read_cycleh always
 jump csr_read_hpmcounter always
 jump csr_read_mie always
@@ -2805,6 +2807,7 @@ jump csr_read_time always
 jump csr_read_timeh always
 jump csr_read_zero always
 jump csr_write_csrs always
+jump csr_write_mcycle always
 jump csr_write_mie always
 jump csr_write_minstret always
 jump csr_write_minstreth always

src/peripherals/debugger.mlog.jinja

@@ -169,7 +169,7 @@ loop:
     set ICACHE_START RAM_END
     op add ICACHE_END ICACHE_START ICACHE_SIZE
 
-    read mcycle {{CSRS}} "{{ 'mcycle'|csr }}"
+    read mcycle {{CPU}} "csr_mcycle"
     read mcycleh {{CSRS}} "{{ 'mcycleh'|csr }}"
     op shl mcycleh mcycleh 32
     op add mcycle mcycle mcycleh