Fix incorrect U-mode timer behaviour

Author: object-Object

asm/timer.s

@@ -0,0 +1,46 @@
+# https://danielmangum.com/posts/risc-v-bytes-timer-interrupts/
+
+.option norvc
+.section .data
+.section .text.init
+.global _start
+
+_start:
+    li a0, 0
+
+    # set timer for 1 second in the future
+    li t0, 0xf0000008
+    li t1, 1000
+    sw t1, 0(t0)
+    sw zero, 4(t0)
+
+    # set up trap vector
+    la t0, mtrap
+    csrw mtvec, t0
+
+    # set mstatus.MPP to U
+    li t0, 0x1800
+    csrc mstatus, t0
+
+    # enable mie.MTIE
+    li t0, 0x80
+    csrs mie, t0
+
+    # jump to user mode
+    la t1, user
+    csrw mepc, t1
+    mret
+
+mtrap:
+    # increment counter
+    addi a0, a0, 1
+
+    # reset time to 0
+    li t0, 0xf0000000
+    sw zero, 0(t0)
+    sw zero, 4(t0)
+
+    mret
+
+user:
+    j user

src/debugger.mlog.jinja

@@ -148,6 +148,11 @@ loop:
     op shl timeh timeh 32
     op add time time timeh
 
+    read mtimecmp CPU "mtimecmp"
+    read mtimecmph CPU "mtimecmph"
+    op shl mtimecmph mtimecmph 32
+    op add mtimecmp mtimecmp mtimecmph
+    
     read instret CSRS "{{ 'instret'|csr }}"
     read instreth CSRS "{{ 'instreth'|csr }}"
     op shl instreth instreth 32
@@ -375,13 +380,16 @@ loop__no_mark_icache:
 
     #{{'\n'}} {{ print(0, 17) }}
 
-    print "cycle   = {0}\n"
-    format cycle
+    print "mtimecmp = {0}\n"
+    format mtimecmp
 
-    print "time    = {0}\n"
+    print "time     = {0}\n"
     format time
 
-    print "instret = {0}\n\n"
+    print "cycle    = {0}\n"
+    format cycle
+
+    print "instret  = {0}\n\n"
     format instret
 
     #{{'\n'}} {{ print(0, 34) }}

src/main.mlog.jinja

@@ -128,24 +128,30 @@ main:
     op equal mtimeh_eq_mtimecmph mtimeh mtimecmph
     op greaterThanEq mtime_ge_mtimecmp mtime mtimecmp
 
-    op and mtip mtimeh_eq_mtimecmph mtime_ge_mtimecmp
-    op or mtip mtip mtimeh_gt_mtimecmph
-    op shl mtip mtip 7
+    op and mip.mtip mtimeh_eq_mtimecmph mtime_ge_mtimecmp
+    op or mip.mtip mip.mtip mtimeh_gt_mtimecmph
+    op shl mip.mtip mip.mtip 7
 
     read mip {{CSRS}} "{{ 'mip'|csr }}"
     op and mip mip 0b11111111111111111111111101111111
-    op or mip mip mtip
+    op or mip mip mip.mtip
     write mip {{CSRS}} "{{ 'mip'|csr }}"
 
     # check if interrupts should fire
 
+    jump main__interrupts_user_mode lessThan privilege_mode 0b11
+    op and mstatus.mie mstatus 0b1000
+    jump main__skip_interrupts equal mstatus.mie 0
+main__interrupts_user_mode:
+
     # timer interrupt
     read mie {{CSRS}} "{{ 'mie'|csr }}"
-    op and mtie mie mtip
+    op and mie.mtie mie mip.mtip
     set mcause 0x80000007 # machine timer interrupt
     set mtval 0
-    jump trap notEqual mtie 0
+    jump trap notEqual mie.mtie 0
 
+main__skip_interrupts:
 main__skip_time_update:
 
     set mtval pc
@@ -334,7 +340,11 @@ default_mtvec_handler:
 
 illegal_instruction:
     set mcause 2
-    set mtval 0 # TODO: return faulting instruction bits?
+    # TODO: return faulting instruction bits?
+    # continue into trap_without_mtval
+
+trap_without_mtval:
+    set mtval 0
     # continue into trap
 
 trap:
@@ -1598,8 +1608,7 @@ ECALL:
     # 0b1000 (8) = ecall from U-mode
     # 0b1011 (11) = ecall from S-mode
     op or mcause 0b1000 privilege_mode
-    set mtval 0
-    jump trap always
+    jump trap_without_mtval always
 
 EBREAK:
     set mcause 3 # breakpoint