Add config for 16x16 memory setup, generate memory sizes with ld K/M in config

Author: object-Object

python/src/mlogv32/preprocessor/app.py

@@ -7,7 +7,7 @@
 
 from mlogv32.preprocessor.extensions import CommentStatement
 
-from . import filters
+from .filters import FILTERS
 
 app = Typer(
     pretty_exceptions_show_locals=False,
@@ -42,7 +42,7 @@ def configs(yaml_path: Path):
     template = env.get_template(data["template"])
 
     for name, args in data["configs"].items():
-        result = template.render(**data["defaults"], **args)
+        result = template.render(**(data["defaults"] | args))
         (output_dir / name).with_suffix(".mlog").write_text(result, "utf-8")
 
 
@@ -59,11 +59,7 @@ def create_jinja_env(template_dir: Path):
             CommentStatement,
         ],
     )
-    env.filters |= {  # pyright: ignore[reportAttributeAccessIssue]
-        "ram_variable": filters.ram_variable,
-        "quote": filters.quote,
-        "csr": filters.csr,
-    }
+    env.filters |= FILTERS
     return env
 
 

python/src/mlogv32/preprocessor/filters.py

@@ -5,6 +5,17 @@
 
 from mlogv32.scripts.ram_proc import VariableFormat
 
+# https://sourceware.org/binutils/docs/ld/Constants.html#Constants
+MEMORY_K = 1024
+MEMORY_M = 1024 * 1024
+
+FILTERS = dict[str, Callable[..., Any]]()
+
+
+def register_filter[**P, R](f: Callable[P, R]) -> Callable[P, R]:
+    FILTERS[f.__name__] = f
+    return f
+
 
 # from hexdoc.jinja.filters
 def make_jinja_exceptions_suck_a_bit_less[**P, R](f: Callable[P, R]) -> Callable[P, R]:
@@ -25,11 +36,13 @@ def wrapper(*args: P.args, **kwargs: P.kwargs):
 
 
 @make_jinja_exceptions_suck_a_bit_less
+@register_filter
 def ram_variable(index: int):
     return VariableFormat.min.get_variable(index)
 
 
 @make_jinja_exceptions_suck_a_bit_less
+@register_filter
 def csr(name: str | int):
     match name:
         case str():
@@ -41,10 +54,21 @@ def csr(name: str | int):
 
 
 @make_jinja_exceptions_suck_a_bit_less
+@register_filter
 def quote(value: Any):
     return f'"{value}"'
 
 
+@make_jinja_exceptions_suck_a_bit_less
+@register_filter
+def memory_size(size: int):
+    if size % MEMORY_M == 0:
+        return f"{size // MEMORY_M}M"
+    if size % MEMORY_K == 0:
+        return f"{size // MEMORY_K}K"
+    return hex(size)
+
+
 CSRS: dict[str, int] = {
     # unprivileged
     "cycle": 0xC00,

rust/examples/webserver/memory.x

@@ -1,7 +1,7 @@
 MEMORY {
-    ROM   (rx)  : ORIGIN = 0x00000000, LENGTH = 0x80000
-    RAM   (rwx) : ORIGIN = 0x80000000, LENGTH = 0x980000 - 0x1000
-    PANIC (rwx) : ORIGIN = 0x80000000 + 0x980000 - 0x1000, LENGTH = 0x1000
+    ROM   (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
+    RAM   (rwx) : ORIGIN = 0x80000000, LENGTH = 3M - 4K
+    PANIC (rwx) : ORIGIN = ORIGIN(RAM) + LENGTH(RAM), LENGTH = 4K
     MMIO  (rw)  : ORIGIN = 0xf0000000, LENGTH = 0x10000000
 }
 

src/config/base.mlog.jinja

@@ -9,9 +9,13 @@
     set MEMORY_Y_OFFSET {{#MEMORY_Y_OFFSET}}  # y offset from this proc to bottom left memory proc
     set MEMORY_WIDTH {{#MEMORY_WIDTH}}  # physical width of the memory procs
 
-    set ROM_SIZE    {{# '%#0x'|format(ROM_ROWS * MEMORY_WIDTH * 16384) }}  # ROM size in bytes (rx)
-    set RAM_SIZE    {{# '%#0x'|format(RAM_ROWS * MEMORY_WIDTH * 16384) }}  # RAM size in bytes (rwx)
-    set ICACHE_SIZE {{# '%#0x'|format(ICACHE_ROWS * MEMORY_WIDTH * 16384) }}  # icache size in bytes
+#%+ set ROM_SIZE = ROM_ROWS * MEMORY_WIDTH * 16384
+#% set RAM_SIZE = RAM_ROWS * MEMORY_WIDTH * 16384
+#% set ICACHE_SIZE = ICACHE_ROWS * MEMORY_WIDTH * 16384
+
+    set ROM_SIZE    {{# '%#0x'|format(ROM_SIZE) }}  # ROM size in bytes ({{ ROM_SIZE|memory_size }})
+    set RAM_SIZE    {{# '%#0x'|format(RAM_SIZE) }}  # RAM size in bytes ({{ RAM_SIZE|memory_size }})
+    set ICACHE_SIZE {{# '%#0x'|format(ICACHE_SIZE) }}  # icache size in bytes ({{ ICACHE_SIZE|memory_size }})
 
     set UART_FIFO_CAPACITY {{#UART_FIFO_CAPACITY}}  # UART TX/RX FIFO capacity in bytes (max 253)
 

src/config/configs.yaml

@@ -3,6 +3,7 @@ template: base.mlog.jinja
 defaults:
   TARGET_IPT: 500000
   BREAKPOINT_ADDRESS: '0x'
+  UART_FIFO_CAPACITY: 253
 
 configs:
   riscv-arch-test:
@@ -12,12 +13,12 @@ configs:
     ROM_ROWS: 9
     RAM_ROWS: 9
     ICACHE_ROWS: 6
-    UART_FIFO_CAPACITY: 253
-  webserver:
+
+  micro:
+    TARGET_IPT: 250000 # we're running two of these at once, so underclock it
     MEMORY_X_OFFSET: -9
-    MEMORY_Y_OFFSET: -23
-    MEMORY_WIDTH: 32
-    ROM_ROWS: 1
-    RAM_ROWS: 19
-    ICACHE_ROWS: 1
-    UART_FIFO_CAPACITY: 253
+    MEMORY_Y_OFFSET: -32
+    MEMORY_WIDTH: 16
+    ROM_ROWS: 2
+    RAM_ROWS: 12
+    ICACHE_ROWS: 2