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This project demonstrates the **design of a 6-Transistor (6T) SRAM memory cell** using the **Electric VLSI Design System**. It includes only the **schematic and layout**—simulation and waveform outputs are not included in this repository.

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6T SRAM Cell CMOS Design with Electric VLSI

6T SRAM Cell
Electric VLSI
Open Source

Welcome to the 6T SRAM Cell CMOS Design repository! This project showcases the design of a 6-Transistor (6T) SRAM memory cell using the Electric VLSI Design System. You can find the schematic and layout files in this repository. Please note that simulation and waveform outputs are not included.

For the latest updates and downloads, visit our Releases section.

Table of Contents

  1. Introduction
  2. Features
  3. Installation
  4. Usage
  5. Design Files
  6. Contributing
  7. License
  8. Contact

Introduction

The 6T SRAM cell is a fundamental building block in modern digital circuits. It provides a compact and efficient way to store data. This project focuses on the design aspects, specifically using the Electric VLSI Design System, which is a powerful tool for integrated circuit design.

Features

  • Schematic Design: Detailed schematic representation of the 6T SRAM cell.
  • Layout Design: Complete layout for manufacturing the SRAM cell.
  • Open Source: All files are freely available for use and modification.
  • Educational Purpose: Aimed at students and professionals looking to understand SRAM design.

Installation

To get started, clone this repository to your local machine:

git clone https://github.com/ogurasek123/6t-sram-cell-cmos-design-electric-vlsi-tool.git

Make sure you have the Electric VLSI Design System installed. You can download it from the official website. Follow the installation instructions provided there.

Usage

After cloning the repository, navigate to the directory containing the design files. Open the schematic and layout files using Electric VLSI.

To simulate the SRAM cell, you will need to set up the simulation environment separately. This project does not include simulation files, but you can create your own based on the provided designs.

Design Files

The design files are organized into two main directories:

  • Schematic: Contains the schematic files for the 6T SRAM cell.
  • Layout: Contains the layout files necessary for fabrication.

You can download the design files from the Releases section. Download the appropriate version and follow the instructions to execute the files.

Contributing

We welcome contributions to this project. If you would like to improve the design or add features, please follow these steps:

  1. Fork the repository.
  2. Create a new branch for your feature.
  3. Make your changes and commit them.
  4. Push your changes to your fork.
  5. Create a pull request.

Please ensure that your contributions align with the goals of this project.

License

This project is licensed under the MIT License. You can freely use, modify, and distribute the design files, but please credit the original authors.

Contact

For any questions or feedback, please reach out to the repository owner. You can also visit the Releases section for updates and information.


Feel free to explore the project and dive into the world of SRAM design. We hope this repository serves as a valuable resource for your studies and projects in circuit design.

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This project demonstrates the **design of a 6-Transistor (6T) SRAM memory cell** using the **Electric VLSI Design System**. It includes only the **schematic and layout**—simulation and waveform outputs are not included in this repository.

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