GitHub - oliverbunting/verilator-unisims: This is mainly a simulation library of xilinx primitives that are verilator compatible.

Name		Name	Last commit message	Last commit date
Latest commit History 32 Commits
.gitignore		.gitignore
BUFG.v		BUFG.v
BUFGMUX.v		BUFGMUX.v
BUFIO2.v		BUFIO2.v
BUFPLL.v		BUFPLL.v
DCM_SP.v		DCM_SP.v
DSP48E2.v		DSP48E2.v
FD.v		FD.v
FDC.v		FDC.v
FDE.v		FDE.v
FDP.v		FDP.v
FDR.v		FDR.v
FDRE.v		FDRE.v
FDS.v		FDS.v
FDSE.v		FDSE.v
GND.v		GND.v
IBUFDS.v		IBUFDS.v
IBUFGDS.v		IBUFGDS.v
IDDR2.v		IDDR2.v
INV.v		INV.v
IOBUF.v		IOBUF.v
IODELAY2.v		IODELAY2.v
ISERDES2.v		ISERDES2.v
LDC.v		LDC.v
LUT1.v		LUT1.v
LUT2.v		LUT2.v
LUT3.v		LUT3.v
LUT4.v		LUT4.v
LUT5.v		LUT5.v
LUT6.v		LUT6.v
LUT6_2.v		LUT6_2.v
MULT_AND.v		MULT_AND.v
MUXCY.v		MUXCY.v
MUXCY_L.v		MUXCY_L.v
MUXF5.v		MUXF5.v
MUXF6.v		MUXF6.v
MUXF7.v		MUXF7.v
OBUFDS.v		OBUFDS.v
ODDR2.v		ODDR2.v
OSERDES2.v		OSERDES2.v
PLL_BASE.v		PLL_BASE.v
RAM16X1D.v		RAM16X1D.v
RAM32X1D.v		RAM32X1D.v
RAMB16BWER.v		RAMB16BWER.v
README		README
SRL16E.v		SRL16E.v
URAM288.v		URAM288.v
VCC.v		VCC.v
XORCY.v		XORCY.v

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This is mainly a simulation library of xilinx primitives that are
verilator compatible.

This is mainly a simulation library of xilinx primitives that are verilator compatible.

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