Add simulator targets to several FPGA Tutorials (#1100)

Author: ajaykumarkannan

DirectProgramming/DPC++/ProjectTemplates/cmake-fpga/README.md

@@ -11,7 +11,7 @@ This code sample is minimal project template for FPGA using the `CMake` build sy
 
 This project is a template designed to help you quickly create your own SYCL*-compliant application for FPGA targets.
 
-The template assumes the use of `CMake` to build your application. The supplied `CMakeLists.txt` file contains the compiler options and libraries needed to compile an application for FPGA targets. 
+The template assumes the use of `CMake` to build your application. The supplied `CMakeLists.txt` file contains the compiler options and libraries needed to compile an application for FPGA targets.
 
 The `main.cpp` source file shows the header files- that you should include and the recommended "device selector" code for targeting the application runtime device.
 
@@ -60,7 +60,7 @@ The basic steps to build and run a sample using VS Code include:
  3. Open a terminal in VS Code (**Terminal > New Terminal**).
  4. Run the sample in the VS Code terminal using the instructions below.
 
-To learn more about the extensions and how to configure the oneAPI environment, see the 
+To learn more about the extensions and how to configure the oneAPI environment, see the
 [Using Visual Studio Code with Intel® oneAPI Toolkits User Guide](https://www.intel.com/content/www/us/en/develop/documentation/using-vs-code-with-intel-oneapi/top.html).
 
 ### On Linux*
@@ -125,7 +125,7 @@ qsub -I -l nodes=1:fpga_runtime:ppn=2 -d .
   |FPGA Runtime (Stratix 10) |`qsub -l nodes=1:fpga_runtime:stratix10:ppn=2 -d .`
   |GPU	                     |`qsub -l nodes=1:gpu:ppn=2 -d .`
   |CPU	                     |`qsub -l nodes=1:xeon:ppn=2 -d .`
-  
+
 
 
 >**Note**: For more information on how to specify compute nodes read, [Launch and manage jobs](https://devcloud.intel.com/oneapi/documentation/job-submission/) in the Intel® DevCloud for oneAPI Documentation.
@@ -143,4 +143,4 @@ Neither compiling nor executing programs on FPGA hardware are supported on the l
 Code samples are licensed under the MIT license. See
 [License.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/License.txt) for details.
 
-Third party program Licenses can be found here: [third-party-programs.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/third-party-programs.txt).
+Third party program Licenses can be found here: [third-party-programs.txt](https://github.com/oneapi-src/oneAPI-samples/blob/master/third-party-programs.txt).

DirectProgramming/DPC++/ProjectTemplates/cmake-fpga/src/CMakeLists.txt

@@ -1,6 +1,7 @@
 set(SOURCE_FILE main.cpp)
 set(TARGET_NAME cmake)
 set(EMULATOR_TARGET ${TARGET_NAME}.fpga_emu)
+set(SIMULATOR_TARGET ${TARGET_NAME}.fpga_sim)
 set(FPGA_TARGET ${TARGET_NAME}.fpga)
 
 
@@ -18,6 +19,8 @@ endif()
 # Compile flags
 set(EMULATOR_COMPILE_FLAGS "-fintelfpga -DFPGA_EMULATOR ")
 set(EMULATOR_LINK_FLAGS    "-fintelfpga ")
+set(SIMULATOR_COMPILE_FLAGS "-fintelfpga -DFPGA_SIMULATOR")
+set(SIMULATOR_LINK_FLAGS    "-fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE_NAME} ${USER_HARDWARE_FLAGS}")
 set(HARDWARE_COMPILE_FLAGS "-fintelfpga")
 set(HARDWARE_LINK_FLAGS    "-fintelfpga -Xshardware -Xstarget=${FPGA_DEVICE_NAME} ${USER_HARDWARE_FLAGS}")
 # use: cmake -D USER_HARDWARE_FLAGS=<flags> to set additional flags for FPGA backend compilation
@@ -29,7 +32,6 @@ add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET})
 set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS ${EMULATOR_COMPILE_FLAGS})
 set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS ${EMULATOR_LINK_FLAGS})
 
-
 # Generate report (without compiling all the way to FPGA hardware)
 set(DEVICE_OBJ_FILE ${TARGET_NAME}_report.a)
 add_custom_target(report DEPENDS ${DEVICE_OBJ_FILE})
@@ -40,6 +42,11 @@ add_custom_command(OUTPUT ${DEVICE_OBJ_FILE}
                    COMMAND ${CMAKE_CXX_COMPILER} ${CMAKE_CXX_FLAGS_LIST} ${HARDWARE_LINK_FLAGS_LIST} -fsycl-link ${SOURCE_FILE} -o ${CMAKE_BINARY_DIR}/${DEVICE_OBJ_FILE}
                    DEPENDS ${SOURCE_FILE})
 
+# FPGA simulator
+add_executable(${SIMULATOR_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE})
+add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET})
+set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS ${SIMULATOR_COMPILE_FLAGS})
+set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS ${SIMULATOR_LINK_FLAGS})
 
 # FPGA hardware
 add_executable(${FPGA_TARGET} EXCLUDE_FROM_ALL ${SOURCE_FILE})
@@ -53,7 +60,12 @@ add_custom_target(run_emu
                   COMMAND ../${TARGET_NAME}.fpga_emu
                   DEPENDS ${TARGET_NAME}.fpga_emu)
 
+# Run FPGA simulator
+add_custom_target(run_sim
+                  COMMAND ../${TARGET_NAME}.fpga_sim
+                  DEPENDS ${TARGET_NAME}.fpga_sim)
+
 # Run FPGA hardware
 add_custom_target(run_hw
-                  COMMAND ../${TARGET_NAME}.fpga_emu
-                  DEPENDS ${TARGET_NAME}.fpga_emu)
+                  COMMAND ../${TARGET_NAME}.fpga
+                  DEPENDS ${TARGET_NAME}.fpga)

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/CMakeLists.txt

@@ -79,7 +79,7 @@ else()
       set(SEED 1)
     endif()
   endif()
-  
+
   set(SEED_FLAG "-Xsseed=${SEED}")
 endif()
 
@@ -97,7 +97,7 @@ endif()
 set(EMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fsycl -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_EMULATOR")
 set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG}")
 set(SIMULATOR_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fsycl -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG} -DFPGA_SIMULATOR")
-set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}")
+set(SIMULATOR_LINK_FLAGS "-fsycl -fintelfpga -Xssimulation -Xsghdl -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}")
 set(HARDWARE_COMPILE_FLAGS "-Wall ${CONSTEXPR_STEPS} ${WIN_FLAG} -fsycl -fintelfpga ${AC_TYPES_FLAG} ${LITERALS_PER_CYCLE_FLAG} ${DECOMPRESS_FORMAT_FLAG}")
 set(REPORT_LINK_FLAGS "-fsycl -fintelfpga -Xshardware ${PROFILE_FLAG} ${FLAT_COMPILE_FLAG} -Xsparallel=2 ${SEED_FLAG} -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS}")
 set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}")
@@ -112,15 +112,6 @@ set_target_properties(${EMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${EMULATOR_CO
 set_target_properties(${EMULATOR_TARGET} PROPERTIES LINK_FLAGS "${EMULATOR_LINK_FLAGS}")
 add_custom_target(fpga_emu DEPENDS ${EMULATOR_TARGET})
 
-###############################################################################
-### FPGA Simulator
-###############################################################################
-add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE})
-target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../include)
-set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}")
-set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}")
-add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET})
-
 ###############################################################################
 ### Generate Report
 ###############################################################################
@@ -133,6 +124,15 @@ set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES COMPILE_FLAGS "${HARDWARE_C
 set_target_properties(${FPGA_EARLY_IMAGE} PROPERTIES LINK_FLAGS "${REPORT_LINK_FLAGS} -fsycl-link=early")
 # fsycl-link=early stops the compiler after RTL generation, before invoking Quartus
 
+###############################################################################
+### FPGA Simulator
+###############################################################################
+add_executable(${SIMULATOR_TARGET} ${SOURCE_FILE})
+target_include_directories(${SIMULATOR_TARGET} PRIVATE ../../../include)
+set_target_properties(${SIMULATOR_TARGET} PROPERTIES COMPILE_FLAGS "${SIMULATOR_COMPILE_FLAGS}")
+set_target_properties(${SIMULATOR_TARGET} PROPERTIES LINK_FLAGS "${SIMULATOR_LINK_FLAGS}")
+add_custom_target(fpga_sim DEPENDS ${SIMULATOR_TARGET})
+
 ###############################################################################
 ### FPGA Hardware
 ###############################################################################

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/common/common.hpp

@@ -187,27 +187,6 @@ auto CTZ(const ac_int<bits, is_signed>& in) {
   return ret;
 }
 
-//
-// Selects a SYCL device using a string. This is typically used to select
-// the FPGA simulator device
-//
-class select_by_string : public sycl::default_selector {
- public:
-  select_by_string(std::string s) : target_name(s) {}
-  virtual int operator()(const sycl::device& device) const {
-    std::string name = device.get_info<sycl::info::device::name>();
-    if (name.find(target_name) != std::string::npos) {
-      // The returned value represents a priority, this number is chosen to be
-      // large to ensure high priority
-      return 10000;
-    }
-    return -1;
-  }
-
- private:
-  std::string target_name;
-};
-
 //
 // Reads 'filename' and returns an array of chars (the bytes of the file)
 //

DirectProgramming/DPC++FPGA/ReferenceDesigns/decompress/src/main.cpp

@@ -128,9 +128,7 @@ int main(int argc, char* argv[]) {
 #if defined(FPGA_EMULATOR)
   sycl::ext::intel::fpga_emulator_selector selector;
 #elif defined(FPGA_SIMULATOR)
-  std::string simulator_device_string =
-      "SimulatorDevice : Multi-process Simulator (aclmsim0)";
-  select_by_string selector = select_by_string{simulator_device_string};
+  sycl::ext::intel::fpga_simulator_selector selector;
 #else
   sycl::ext::intel::fpga_selector selector;
 #endif

DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt

@@ -91,10 +91,10 @@ endif()
 #    For this reason, FPGA backend flags must be passed as link flags in CMake.
 set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fsycl -fintelfpga -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -DFPGA_EMULATOR")
 set(EMULATOR_LINK_FLAGS "-fsycl -fintelfpga ${AC_TYPES_FLAG} ${ENABLE_USM}")
-set(SIMULATOR_COMPILE_FLAGS "-Wall -fsycl -fintelfpga -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG}")
-set(SIMULATOR_LINK_FLAGS "-Wall -fsycl -fintelfpga -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -Xssimulation -Xsghdl")
+set(SIMULATOR_COMPILE_FLAGS "${WIN_FLAG} -Wall -fsycl -fintelfpga -fbracket-depth=512 ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -DFPGA_SIMULATOR")
 set(HARDWARE_COMPILE_FLAGS "${WIN_FLAG} -fbracket-depth=512 -fsycl -fintelfpga ${AC_TYPES_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG}")
 set(REPORT_LINK_FLAGS "-Wall -fsycl -fintelfpga -Xshardware -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} ${PROFILE_FLAG} -Xsparallel=2 -Xstarget=${FPGA_DEVICE} ${USER_HARDWARE_FLAGS} ${UDP_LINK_FLAGS}")
+set(SIMULATOR_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG} -Xssimulation -Xsghdl")
 set(HARDWARE_LINK_FLAGS "${REPORT_LINK_FLAGS} ${AC_TYPES_FLAG}")
 # use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA backend compilation
 

DirectProgramming/DPC++FPGA/ReferenceDesigns/qri/sample.json

@@ -74,4 +74,4 @@
     ]
   },
   "expertise": "Reference Designs and End to End"
-}
+}