AXI4 arlock/awlock has width of 2 bits instead of 1 bit

[johanpel]

According to AXI4 spec, arlock/awlock signals should be of width 1. However, in (as far as I can tell) all sources that contain an AXI port, they are of width 2.

At the action_wrapper level in the HDL flow, this causes a very minor nuisance when connecting AXI4 IP to the wrapper host memory port.

I can see that the signal is not used by the PSL/AXI shim (i.e. all accesses are normal accesses) at all. Not sure how this relates to the HLS flow.

[jsvogt]

@ThomasFuchs I know this is no "must fix". What would break if we changed all ports to width 1?
Does this have to do with the problem to have "1 downto 0" for 2-bit vs. "0 to 0" for single-bit "vectors"?