Search results

Cannot simulate with QuestaSim

Status: Open.

#891 In open-power/snap;

· BasF0 opened on Jul 17, 2019

Using Multiple Banks in DDR to Enable Multiple Read/Write at Same Cycle

nice to have

question

Status: Open.

#890 In open-power/snap;

· yuanm2 opened on Jul 11, 2019

SW Action not running when using snap_action_start specific API

nice to have

Status: Open.

#888 In open-power/snap;

· sinitame opened on Jul 2, 2019

bus error on deployment of an action that passes pslse

Status: Open.

#882 In open-power/snap;

· diamantopoulos opened on May 10, 2019

Support simulating SNAP actions using Vivado WebPACK

nice to have

Status: Open.

#821 In open-power/snap;

· rs22 opened on Sep 26, 2018

make clean conflicts with per action "user IP"

enhancement

verify

Status: Open.

#798 In open-power/snap;

· david-mle opened on Aug 17, 2018

SR10441909: xsim: writememh() works in combination with sformat() and readmemh() does not

bug

in progress

Xilinx_SRs

Status: Open.

#766 In open-power/snap;

· fhaverkamp opened on Jul 6, 2018

AXI4 arlock/awlock has width of 2 bits instead of 1 bit

bug

nice to have

Status: Open.

#758 In open-power/snap;

· johanpel opened on Jun 27, 2018

Integrate AXI protocol checkers

enhancement

Status: Open.

#756 In open-power/snap;

· johanpel opened on Jun 26, 2018

NVMe: high level model - review findings

enhancement

Status: Open.

#748 In open-power/snap;

· boekholt opened on Jun 12, 2018

NVMe: High-level model for SNAP NVMe Support multiple operations in parallel

enhancement

Status: Open.

#739 In open-power/snap;

· fhaverkamp opened on May 16, 2018

Enable the 2nd DRAM controller for ADKU3 and S121B cards

enhancement

Status: Open.

#619 In open-power/snap;

· jsvogt opened on Feb 8, 2018