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Cannot simulate with QuestaSim #891

@BasF0

Description

@BasF0

When trying to start simulation of an example with QuestaSim it fails with message:

# ** Error (suppressible): (vsim-19) Failed to access library 'work' at "work".
# No such file or directory. (errno = ENOENT)
# Error loading design

In the compile_questa.log the first error is:

** Error: ../../hdl/core/snap_core_types.vhd(257): near "address": (vcom-1576) expecting ':'.

Which fails to compile top, thus failing simulation. The line mentioned is a comment, so I'm not sure what is going on there.

occurs on latest master: 1507cb1
also tried one of the early commits mentioning questasim, same error: 1ebc208

Tried with FPGA= Xilinx U200, Nallatech 250S, hdl_helloworld, hls_helloworld examples..

Vivado v2018.3, QuestaSim-64 10.6a

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