Using Multiple Banks in DDR to Enable Multiple Read/Write at Same Cycle

[yuanm2]

To use multiple banks/controlers in the DDR to enable simultaneous reads/writes, what should I make changes of the SW/HW actions in the CAPI SNAP. I am thinking to add another DDR port beside the following one:
// DDR memory Interface
#pragma HLS INTERFACE m_axi port=d_ddrmem bundle=card_mem0 offset=slave depth=512 max_read_burst_length=64 max_write_burst_length=64
#pragma HLS INTERFACE s_axilite port=d_ddrmem bundle=ctrl_reg offset=0x050

Besides, should I make modifications in the makefile following what sDx tool suggests? (https://www.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/tom1504034303746.html)

[bmesnet]

Hi @yuanm2
Issue #619 may partially answer to your question.
In our designs, you have noted that we have indeed implemented only 1 Bank (or channel) while most cards have several banks as described here (N250S+ is one of the rare card which has only 1 DDR bank). The main reason was that depending on user's needs, there was 2 options; first is to just extend the size of the first bank by adding this 2nd bank on the same DDR driver. The other option was to use 2 drivers in parallel to have a higher throughput. This last option means that you will need to duplicate the DDR driver in place and this will take twice the place in the design.
This may highlight that the change to implement in SNAP is not just the HLS ports to change as you pointed it, but you need to change the logic to duplicate this DDR driver and connect it as a new DDR port on the action.
As for an opensource project, you are very welcome to add your contribution by implementing it and add it to the SNAP design.