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| Clock Domains | ||
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| The Core-v-mcu has three major clock domains that are all derived from the input reference clock. |
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CORE-V-MCU shouldl be all upper-case.
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| - The input reference clock(i.e ref_clk_i) is assumed to be 10 MHz. | ||
| - There are 3 major subsystems in CORE_V_MCU and each of these uses a different set of clocks for its working. |
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| The output of the PLL is divided by 10-bit divisors to create the SoC clock, the peripherial Clock and the Primary FPGA clock. | ||
| An Additional divisor reduces the input reference clock. | ||
| The working of APB_PLL is explained in specification with all the IPs of APB subsystem. |
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I assume you are referring to the apb_fll_if chapter. There is some confusion here. I am not sure the apb_fll_if module is used in the MCU. The confusion seems to stem from the way that the soc_peripherals module instantiates the apb_pll. The instance name of is apb_fll_if_i which implies that is it an instance of apb_fll_if, but it is not.
It will be difficult to resolve this over GitHub - let's discuss in person.
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Hi @cst-rameez, I am confused about a few things, please see my comments.
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Updated the diagram to show how various clocks are connected in the subsystem.