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author
Fei Yang
committed
Merge branch 'master' into riscv-port
2 parents 7790205 + 0bddd8a commit d9b892c

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343 files changed

+10013
-3618
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343 files changed

+10013
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lines changed

‎src/hotspot/cpu/aarch64/aarch64.ad‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8565,10 +8565,10 @@ instruct popCountI(iRegINoSp dst, iRegIorL2I src, vRegF tmp) %{
85658565
"mov $dst, $tmp\t# vector (1D)" %}
85668566
ins_encode %{
85678567
__ movw($src$$Register, $src$$Register); // ensure top 32 bits 0
8568-
__ mov($tmp$$FloatRegister, __ T1D, 0, $src$$Register);
8568+
__ mov($tmp$$FloatRegister, __ D, 0, $src$$Register);
85698569
__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
85708570
__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8571-
__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
8571+
__ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
85728572
%}
85738573

85748574
ins_pipe(pipe_class_default);
@@ -8590,7 +8590,7 @@ instruct popCountI_mem(iRegINoSp dst, memory4 mem, vRegF tmp) %{
85908590
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
85918591
__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
85928592
__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8593-
__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
8593+
__ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
85948594
%}
85958595

85968596
ins_pipe(pipe_class_default);
@@ -8608,10 +8608,10 @@ instruct popCountL(iRegINoSp dst, iRegL src, vRegD tmp) %{
86088608
"addv $tmp, $tmp\t# vector (8B)\n\t"
86098609
"mov $dst, $tmp\t# vector (1D)" %}
86108610
ins_encode %{
8611-
__ mov($tmp$$FloatRegister, __ T1D, 0, $src$$Register);
8611+
__ mov($tmp$$FloatRegister, __ D, 0, $src$$Register);
86128612
__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
86138613
__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8614-
__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
8614+
__ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
86158615
%}
86168616

86178617
ins_pipe(pipe_class_default);
@@ -8633,7 +8633,7 @@ instruct popCountL_mem(iRegINoSp dst, memory8 mem, vRegD tmp) %{
86338633
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
86348634
__ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
86358635
__ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
8636-
__ mov($dst$$Register, $tmp$$FloatRegister, __ T1D, 0);
8636+
__ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
86378637
%}
86388638

86398639
ins_pipe(pipe_class_default);

‎src/hotspot/cpu/aarch64/aarch64_neon.ad‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -511,7 +511,7 @@ instruct vcvt2Dto2I(vecD dst, vecX src)
511511
"fcvtzdw rscratch1, $src\n\t"
512512
"fcvtzdw rscratch2, $dst\n\t"
513513
"fmovs $dst, rscratch1\n\t"
514-
"mov $dst, T2S, 1, rscratch2\t#convert 2D to 2I vector"
514+
"mov $dst, S, 1, rscratch2\t#convert 2D to 2I vector"
515515
%}
516516
ins_encode %{
517517
__ ins(as_FloatRegister($dst$$reg), __ D, as_FloatRegister($src$$reg), 0, 1);
@@ -520,7 +520,7 @@ instruct vcvt2Dto2I(vecD dst, vecX src)
520520
__ fcvtzdw(rscratch1, as_FloatRegister($src$$reg));
521521
__ fcvtzdw(rscratch2, as_FloatRegister($dst$$reg));
522522
__ fmovs(as_FloatRegister($dst$$reg), rscratch1);
523-
__ mov(as_FloatRegister($dst$$reg), __ T2S, 1, rscratch2);
523+
__ mov(as_FloatRegister($dst$$reg), __ S, 1, rscratch2);
524524
%}
525525
ins_pipe(pipe_slow);
526526
%}
@@ -1703,13 +1703,13 @@ instruct insert8B(vecD dst, vecD src, iRegIorL2I val, immI idx)
17031703
match(Set dst (VectorInsert (Binary src val) idx));
17041704
ins_cost(INSN_COST);
17051705
format %{ "orr $dst, T8B, $src, $src\n\t"
1706-
"mov $dst, T8B, $idx, $val\t# insert into vector(8B)" %}
1706+
"mov $dst, B, $idx, $val\t# insert into vector(8B)" %}
17071707
ins_encode %{
17081708
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
17091709
__ orr(as_FloatRegister($dst$$reg), __ T8B,
17101710
as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
17111711
}
1712-
__ mov(as_FloatRegister($dst$$reg), __ T8B, $idx$$constant, $val$$Register);
1712+
__ mov(as_FloatRegister($dst$$reg), __ B, $idx$$constant, $val$$Register);
17131713
%}
17141714
ins_pipe(pipe_slow);
17151715
%}
@@ -1720,13 +1720,13 @@ instruct insert16B(vecX dst, vecX src, iRegIorL2I val, immI idx)
17201720
match(Set dst (VectorInsert (Binary src val) idx));
17211721
ins_cost(INSN_COST);
17221722
format %{ "orr $dst, T16B, $src, $src\n\t"
1723-
"mov $dst, T16B, $idx, $val\t# insert into vector(16B)" %}
1723+
"mov $dst, B, $idx, $val\t# insert into vector(16B)" %}
17241724
ins_encode %{
17251725
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
17261726
__ orr(as_FloatRegister($dst$$reg), __ T16B,
17271727
as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
17281728
}
1729-
__ mov(as_FloatRegister($dst$$reg), __ T16B, $idx$$constant, $val$$Register);
1729+
__ mov(as_FloatRegister($dst$$reg), __ B, $idx$$constant, $val$$Register);
17301730
%}
17311731
ins_pipe(pipe_slow);
17321732
%}
@@ -1737,13 +1737,13 @@ instruct insert4S(vecD dst, vecD src, iRegIorL2I val, immI idx)
17371737
match(Set dst (VectorInsert (Binary src val) idx));
17381738
ins_cost(INSN_COST);
17391739
format %{ "orr $dst, T8B, $src, $src\n\t"
1740-
"mov $dst, T4H, $idx, $val\t# insert into vector(4S)" %}
1740+
"mov $dst, H, $idx, $val\t# insert into vector(4S)" %}
17411741
ins_encode %{
17421742
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
17431743
__ orr(as_FloatRegister($dst$$reg), __ T8B,
17441744
as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
17451745
}
1746-
__ mov(as_FloatRegister($dst$$reg), __ T4H, $idx$$constant, $val$$Register);
1746+
__ mov(as_FloatRegister($dst$$reg), __ H, $idx$$constant, $val$$Register);
17471747
%}
17481748
ins_pipe(pipe_slow);
17491749
%}
@@ -1754,13 +1754,13 @@ instruct insert8S(vecX dst, vecX src, iRegIorL2I val, immI idx)
17541754
match(Set dst (VectorInsert (Binary src val) idx));
17551755
ins_cost(INSN_COST);
17561756
format %{ "orr $dst, T16B, $src, $src\n\t"
1757-
"mov $dst, T8H, $idx, $val\t# insert into vector(8S)" %}
1757+
"mov $dst, H, $idx, $val\t# insert into vector(8S)" %}
17581758
ins_encode %{
17591759
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
17601760
__ orr(as_FloatRegister($dst$$reg), __ T16B,
17611761
as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
17621762
}
1763-
__ mov(as_FloatRegister($dst$$reg), __ T8H, $idx$$constant, $val$$Register);
1763+
__ mov(as_FloatRegister($dst$$reg), __ H, $idx$$constant, $val$$Register);
17641764
%}
17651765
ins_pipe(pipe_slow);
17661766
%}
@@ -1771,13 +1771,13 @@ instruct insert2I(vecD dst, vecD src, iRegIorL2I val, immI idx)
17711771
match(Set dst (VectorInsert (Binary src val) idx));
17721772
ins_cost(INSN_COST);
17731773
format %{ "orr $dst, T8B, $src, $src\n\t"
1774-
"mov $dst, T2S, $idx, $val\t# insert into vector(2I)" %}
1774+
"mov $dst, S, $idx, $val\t# insert into vector(2I)" %}
17751775
ins_encode %{
17761776
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
17771777
__ orr(as_FloatRegister($dst$$reg), __ T8B,
17781778
as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
17791779
}
1780-
__ mov(as_FloatRegister($dst$$reg), __ T2S, $idx$$constant, $val$$Register);
1780+
__ mov(as_FloatRegister($dst$$reg), __ S, $idx$$constant, $val$$Register);
17811781
%}
17821782
ins_pipe(pipe_slow);
17831783
%}
@@ -1788,13 +1788,13 @@ instruct insert4I(vecX dst, vecX src, iRegIorL2I val, immI idx)
17881788
match(Set dst (VectorInsert (Binary src val) idx));
17891789
ins_cost(INSN_COST);
17901790
format %{ "orr $dst, T16B, $src, $src\n\t"
1791-
"mov $dst, T4S, $idx, $val\t# insert into vector(4I)" %}
1791+
"mov $dst, S, $idx, $val\t# insert into vector(4I)" %}
17921792
ins_encode %{
17931793
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
17941794
__ orr(as_FloatRegister($dst$$reg), __ T16B,
17951795
as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
17961796
}
1797-
__ mov(as_FloatRegister($dst$$reg), __ T4S, $idx$$constant, $val$$Register);
1797+
__ mov(as_FloatRegister($dst$$reg), __ S, $idx$$constant, $val$$Register);
17981798
%}
17991799
ins_pipe(pipe_slow);
18001800
%}
@@ -1805,13 +1805,13 @@ instruct insert2L(vecX dst, vecX src, iRegL val, immI idx)
18051805
match(Set dst (VectorInsert (Binary src val) idx));
18061806
ins_cost(INSN_COST);
18071807
format %{ "orr $dst, T16B, $src, $src\n\t"
1808-
"mov $dst, T2D, $idx, $val\t# insert into vector(2L)" %}
1808+
"mov $dst, D, $idx, $val\t# insert into vector(2L)" %}
18091809
ins_encode %{
18101810
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
18111811
__ orr(as_FloatRegister($dst$$reg), __ T16B,
18121812
as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
18131813
}
1814-
__ mov(as_FloatRegister($dst$$reg), __ T2D, $idx$$constant, $val$$Register);
1814+
__ mov(as_FloatRegister($dst$$reg), __ D, $idx$$constant, $val$$Register);
18151815
%}
18161816
ins_pipe(pipe_slow);
18171817
%}
@@ -2044,11 +2044,11 @@ instruct vmul2L(vecX dst, vecX src1, vecX src2, iRegLNoSp tmp1, iRegLNoSp tmp2)
20442044
__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 0);
20452045
__ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 0);
20462046
__ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
2047-
__ mov(as_FloatRegister($dst$$reg), __ T2D, 0, $tmp2$$Register);
2047+
__ mov(as_FloatRegister($dst$$reg), __ D, 0, $tmp2$$Register);
20482048
__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 1);
20492049
__ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 1);
20502050
__ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
2051-
__ mov(as_FloatRegister($dst$$reg), __ T2D, 1, $tmp2$$Register);
2051+
__ mov(as_FloatRegister($dst$$reg), __ D, 1, $tmp2$$Register);
20522052
%}
20532053
ins_pipe(pipe_slow);
20542054
%}

‎src/hotspot/cpu/aarch64/aarch64_neon_ad.m4‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -296,7 +296,7 @@ instruct vcvt2Dto2I(vecD dst, vecX src)
296296
"fcvtzdw rscratch1, $src\n\t"
297297
"fcvtzdw rscratch2, $dst\n\t"
298298
"fmovs $dst, rscratch1\n\t"
299-
"mov $dst, T2S, 1, rscratch2\t#convert 2D to 2I vector"
299+
"mov $dst, S, 1, rscratch2\t#convert 2D to 2I vector"
300300
%}
301301
ins_encode %{
302302
__ ins(as_FloatRegister($dst$$reg), __ D, as_FloatRegister($src$$reg), 0, 1);
@@ -305,7 +305,7 @@ instruct vcvt2Dto2I(vecD dst, vecX src)
305305
__ fcvtzdw(rscratch1, as_FloatRegister($src$$reg));
306306
__ fcvtzdw(rscratch2, as_FloatRegister($dst$$reg));
307307
__ fmovs(as_FloatRegister($dst$$reg), rscratch1);
308-
__ mov(as_FloatRegister($dst$$reg), __ T2S, 1, rscratch2);
308+
__ mov(as_FloatRegister($dst$$reg), __ S, 1, rscratch2);
309309
%}
310310
ins_pipe(pipe_slow);
311311
%}
@@ -868,13 +868,13 @@ instruct insert$1$2`'(vec$3 dst, vec$3 src, iReg$4`'ORL2I($4) val, immI idx)
868868
match(Set dst (VectorInsert (Binary src val) idx));
869869
ins_cost(INSN_COST);
870870
format %{ "orr $dst, T$5, $src, $src\n\t"
871-
"mov $dst, T$1`'iTYPE2SIMD($2), $idx, $val\t# insert into vector($1$2)" %}
871+
"mov $dst, iTYPE2SIMD($2), $idx, $val\t# insert into vector($1$2)" %}
872872
ins_encode %{
873873
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
874874
__ orr(as_FloatRegister($dst$$reg), __ T$5,
875875
as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
876876
}
877-
__ mov(as_FloatRegister($dst$$reg), __ T$1`'iTYPE2SIMD($2), $idx$$constant, $val$$Register);
877+
__ mov(as_FloatRegister($dst$$reg), __ iTYPE2SIMD($2), $idx$$constant, $val$$Register);
878878
%}
879879
ins_pipe(pipe_slow);
880880
%}')dnl
@@ -1003,11 +1003,11 @@ instruct vmul2L(vecX dst, vecX src1, vecX src2, iRegLNoSp tmp1, iRegLNoSp tmp2)
10031003
__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 0);
10041004
__ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 0);
10051005
__ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
1006-
__ mov(as_FloatRegister($dst$$reg), __ T2D, 0, $tmp2$$Register);
1006+
__ mov(as_FloatRegister($dst$$reg), __ D, 0, $tmp2$$Register);
10071007
__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 1);
10081008
__ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 1);
10091009
__ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
1010-
__ mov(as_FloatRegister($dst$$reg), __ T2D, 1, $tmp2$$Register);
1010+
__ mov(as_FloatRegister($dst$$reg), __ D, 1, $tmp2$$Register);
10111011
%}
10121012
ins_pipe(pipe_slow);
10131013
%}

‎src/hotspot/cpu/aarch64/assembler_aarch64.hpp‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2756,20 +2756,18 @@ void mvnw(Register Rd, Register Rm,
27562756

27572757
// Move from general purpose register
27582758
// mov Vd.T[index], Rn
2759-
void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2759+
void mov(FloatRegister Vd, SIMD_RegVariant T, int index, Register Xn) {
2760+
guarantee(T != Q, "invalid register variant");
27602761
starti;
2761-
f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2762+
f(0b01001110000, 31, 21), f(((1 << T) | (index << (T + 1))), 20, 16);
27622763
f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
27632764
}
27642765

27652766
// Move to general purpose register
27662767
// mov Rd, Vn.T[index]
2767-
void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2768-
guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported");
2769-
starti;
2770-
f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2771-
f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2772-
f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2768+
void mov(Register Xd, FloatRegister Vn, SIMD_RegVariant T, int index) {
2769+
guarantee(T == S || T == D, "invalid register variant");
2770+
umov(Xd, Vn, T, index);
27732771
}
27742772

27752773
private:

‎src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3367,7 +3367,7 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
33673367
ld1r(v5, T2D, post(tmp, 8));
33683368
ld1r(v6, T2D, post(tmp, 8));
33693369
ld1r(v7, T2D, post(tmp, 8));
3370-
mov(v16, T4S, 0, crc);
3370+
mov(v16, S, 0, crc);
33713371

33723372
eor(v0, T16B, v0, v16);
33733373
sub(len, len, 64);
@@ -3471,16 +3471,16 @@ void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
34713471
br(Assembler::GE, L_fold);
34723472

34733473
mov(crc, 0);
3474-
mov(tmp, v0, T1D, 0);
3474+
mov(tmp, v0, D, 0);
34753475
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
34763476
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3477-
mov(tmp, v0, T1D, 1);
3477+
mov(tmp, v0, D, 1);
34783478
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
34793479
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3480-
mov(tmp, v1, T1D, 0);
3480+
mov(tmp, v1, D, 0);
34813481
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
34823482
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
3483-
mov(tmp, v1, T1D, 1);
3483+
mov(tmp, v1, D, 1);
34843484
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
34853485
update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
34863486

‎src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6397,6 +6397,18 @@ class StubGenerator: public StubCodeGenerator {
63976397
return start;
63986398
}
63996399

6400+
// Support for spin waits.
6401+
address generate_spin_wait() {
6402+
__ align(CodeEntryAlignment);
6403+
StubCodeMark mark(this, "StubRoutines", "spin_wait");
6404+
address start = __ pc();
6405+
6406+
__ spin_wait();
6407+
__ ret(lr);
6408+
6409+
return start;
6410+
}
6411+
64006412
#ifdef LINUX
64016413

64026414
// ARMv8.1 LSE versions of the atomic stubs used by Atomic::PlatformXX.
@@ -7715,6 +7727,8 @@ class StubGenerator: public StubCodeGenerator {
77157727
StubRoutines::_updateBytesAdler32 = generate_updateBytesAdler32();
77167728
}
77177729

7730+
StubRoutines::aarch64::_spin_wait = generate_spin_wait();
7731+
77187732
#ifdef LINUX
77197733

77207734
generate_atomic_entry_points();

‎src/hotspot/cpu/aarch64/stubRoutines_aarch64.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,10 @@ address StubRoutines::aarch64::_string_indexof_linear_uu = NULL;
5757
address StubRoutines::aarch64::_string_indexof_linear_ul = NULL;
5858
address StubRoutines::aarch64::_large_byte_array_inflate = NULL;
5959
address StubRoutines::aarch64::_method_entry_barrier = NULL;
60+
61+
static void empty_spin_wait() { }
62+
address StubRoutines::aarch64::_spin_wait = CAST_FROM_FN_PTR(address, empty_spin_wait);
63+
6064
bool StubRoutines::aarch64::_completed = false;
6165

6266
/**

‎src/hotspot/cpu/aarch64/stubRoutines_aarch64.hpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,8 @@ class aarch64 {
7272

7373
static address _method_entry_barrier;
7474

75+
static address _spin_wait;
76+
7577
static bool _completed;
7678

7779
public:
@@ -177,6 +179,10 @@ class aarch64 {
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return _method_entry_barrier;
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}
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182+
static address spin_wait() {
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return _spin_wait;
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}
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static bool complete() {
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return _completed;
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}

‎src/hotspot/cpu/aarch64/vm_version_aarch64.cpp‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -488,3 +488,22 @@ void VM_Version::initialize() {
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_spin_wait = get_spin_wait_desc();
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}
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void VM_Version::initialize_cpu_information(void) {
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// do nothing if cpu info has been initialized
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if (_initialized) {
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return;
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}
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_no_of_cores = os::processor_count();
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_no_of_threads = _no_of_cores;
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_no_of_sockets = _no_of_cores;
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snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64");
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int desc_len = snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 ");
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get_compatible_board(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len);
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desc_len = (int)strlen(_cpu_desc);
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snprintf(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len, " %s", _features_string);
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_initialized = true;
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}

‎src/hotspot/cpu/aarch64/vm_version_aarch64.hpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -153,6 +153,9 @@ class VM_Version : public Abstract_VM_Version {
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// Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
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static bool is_cpu_emulated();
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#endif
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static void initialize_cpu_information(void);
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};
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#endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP

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