Verilator test bench for the 'vscale-generic' system

[rjfnobre]

Any special reason why there is no Verilator test bench for the 'vscale-generic' system, as there is for the 'or1200-generic' system (or1200-generic/bench/verilator/tb.cpp)?

Is there a way to simulate a system with a VScale RISCV core that is capable of executing code compiled with GCC for the RISCV target?

Thanks in advance!

[olofk]

The simple reason is that no one has written a testbench :)

It should be pretty trivial though, and even if there isn't a verilator testbench available, you can still use other simulators even though it won't be as fast

[olofk]

ok, I made a quick'n'dirty verilator testbench now starting from the one in mor1kx-generic. It needs some extra love, and doesn't stop unless you hit Ctrl-C, but at least I can load an elf file compiled with gcc and make it print hello world!

If you want to try it yourself, you can use the testbench and elf file from here and save the tb to vscale-generic/bench/verilator/tb.cpp, add this section to vscale-generic.core

[verilator]
depend = verilator_tb_utils
verilator_options = -Wno-fatal --trace -GBOOTROM_FILE="\"../../src/vscale-generic_0/sw/bootrom.vh\""
tb_toplevel   = bench/verilator/tb.cpp
top_module    = vscale_top

and run with fusesoc sim --sim=verilator vscale_generic --elf-load=/absolute/path/to/hello_uart-wb_vscale.elf

I have unfortunately no good ideas how to create your own elf files for this system, since I was given that elf file from the creator of wb_vscale (the version of vscale with wishbone ports). At least it might get you started. Let me know if I can be of further assistance

[rjfnobre]

Thanks again!

I changed from '-GBOOTROM_FILE' to 'BOOTROM_FILE' as verilator said there was no option with that name.

I get this when executing:
fusesoc sim --sim=verilator vscale-generic

ERROR: Failed to build simulation model
ERROR: "/opt/verilator-3.882/bin/verilator --cc -f input.vc --top-module vscale_top --exe -LDFLAGS " -Wl,--start-group /home/ricardo/test_vscale/build/vscale-generic/sim-verilator/elf-loader.a /home/ricardo/test_vscale/build/vscale-generic/sim-verilator/verilator_tb_utils.a -Wl,--end-group -lelf " -CFLAGS -I/home/ricardo/test_vscale/build/vscale-generic/src/elf-loader/ -CFLAGS -I/home/ricardo/test_vscale/build/vscale-generic/src/verilator_tb_utils/ -CFLAGS -I/home/ricardo/test_vscale/build/vscale-generic/sim-verilator/bench/verilator -CFLAGS -I/home/ricardo/test_vscale/build/vscale-generic/src /home/ricardo/test_vscale/build/vscale-generic/src/vscale-generic/bench/verilator/tb.cpp -Wno-fatal --trace BOOTROM_FILE=""/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh""" exited with an error code.
ERROR: See /home/ricardo/test_vscale/build/vscale-generic/sim-verilator/verilator.log for details.

The log file contains:
%Error: Cannot find file containing module: BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"
%Error: Looked in:
%Error: ../src/verilog_utils//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"
%Error: ../src/verilog_utils//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".v
%Error: ../src/verilog_utils//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".sv
%Error: ../src/vscale-generic/sw/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"
%Error: ../src/vscale-generic/sw/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".v
%Error: ../src/vscale-generic/sw/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".sv
%Error: ../src/uart16550-1.5.4/rtl/verilog/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"
%Error: ../src/uart16550-1.5.4/rtl/verilog/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".v
%Error: ../src/uart16550-1.5.4/rtl/verilog/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".sv
%Error: ../src/wb_common//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"
%Error: ../src/wb_common//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".v
%Error: ../src/wb_common//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".sv
%Error: ../src/or1k_bootloaders-0.9//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"
%Error: ../src/or1k_bootloaders-0.9//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".v
%Error: ../src/or1k_bootloaders-0.9//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".sv
%Error: ../src/wb_riscvscale//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"
%Error: ../src/wb_riscvscale//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".v
%Error: ../src/wb_riscvscale//BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".sv
%Error: ../src/vscale-generic/rtl/verilog/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"
%Error: ../src/vscale-generic/rtl/verilog/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".v
%Error: ../src/vscale-generic/rtl/verilog/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".sv
%Error: BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"
%Error: BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".v
%Error: BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".sv
%Error: obj_dir/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"
%Error: obj_dir/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".v
%Error: obj_dir/BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh".sv
%Error: Exiting due to 29 error(s)
%Error: Command Failed /opt/verilator-3.882/bin/verilator_bin --cc -f input.vc --top-module vscale_top --exe -LDFLAGS ' -Wl,--start-group /home/ricardo/test_vscale/build/vscale-generic/sim-verilator/elf-loader.a /home/ricardo/test_vscale/build/vscale-generic/sim-verilator/verilator_tb_utils.a -Wl,--end-group -lelf ' -CFLAGS -I/home/ricardo/test_vscale/build/vscale-generic/src/elf-loader/ -CFLAGS -I/home/ricardo/test_vscale/build/vscale-generic/src/verilator_tb_utils/ -CFLAGS -I/home/ricardo/test_vscale/build/vscale-generic/sim-verilator/bench/verilator -CFLAGS -I/home/ricardo/test_vscale/build/vscale-generic/src /home/ricardo/test_vscale/build/vscale-generic/src/vscale-generic/bench/verilator/tb.cpp -Wno-fatal --trace 'BOOTROM_FILE="/opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh"'

[olofk]

Ah. It might be that your version of Verilator is too old. The support for setting top-level parameters was added quite recently to verilator. If you're unable to use a newer version of verilator, you might get around this by removing the -GBOOTROM_FILE stuff from the .core file, and instead set the BOOTROM_FILE parameter to "../../src/vscale-generic_0/sw/bootrom.vh" directly in vscale_top.v

[rjfnobre]

I just updated verilator and now it does not complain about '-GBOOTROM_FILE'.

Now I have:
ERROR: "g++ -c -I/home/ricardo/test_vscale/build/vscale-generic/src -I/home/ricardo/test_vscale/build/vscale-generic/src/elf-loader/ -I/home/ricardo/test_vscale/build/vscale-generic/src/verilator_tb_utils/ -I/home/ricardo/test_vscale/build/vscale-generic/sim-verilator/bench/verilator -I/home/ricardo/test_vscale/build/vscale-generic/src -Iobj_dir -I/opt/verilator/include -I/opt/verilator/include/vltstd /home/ricardo/test_vscale/build/vscale-generic/src/verilator_tb_utils/verilator_tb_utils.cpp" exited with an error code.

the log file:
In file included from /home/ricardo/test_vscale/build/vscale-generic/src/verilator_tb_utils/verilator_tb_utils.cpp:7:0:
/home/ricardo/test_vscale/build/vscale-generic/src/verilator_tb_utils/verilator_tb_utils.h:5:23: fatal error: verilated.h: No such file or directory
#include <verilated.h>

[rjfnobre]

Just did:
sudo cp -a /opt/verilator/share/verilator/include /opt/verilator/

And now I go a little further.

INFO: Building verilator executable:
Can't open perl script "/opt/verilator/bin/verilator_includer": No such file or directory
Can't open perl script "/opt/verilator/bin/verilator_includer": No such file or directory
make: *** [Vvscale_top__ALLcls.cpp] Error 2
make: *** Waiting for unfinished jobs....
make: *** [Vvscale_top__ALLsup.cpp] Error 2
ERROR: Failed to build simulation model
ERROR: "make -f Vvscale_top.mk -j 16 Vvscale_top" exited with an error code.
ERROR: See stderr for details.

[rjfnobre]

Solved it with:
sudo cp /opt/verilator/share/verilator/bin/verilator_includer /opt/verilator/bin/

Now I get:
INFO: Starting Verilator:

INFO: Compiling elf-loader.c
ar: creating elf-loader.a
a - elf-loader.o

INFO: Compiling verilator_tb_utils.cpp
INFO: Compiling jtagServer.cpp
ar: creating verilator_tb_utils.a
a - verilator_tb_utils.o
a - jtagServer.o

INFO: Building verilator executable:
ar: creating Vvscale_top__ALL.a
INFO: Running simulation
Loading /home/ricardo/test_vscale/hello_uart-wb_vscale.elf
Program header 0: addr 0x00000000, size 0x00000520
Preloading boot ROM from /opt/orpsoc-cores/systems/vscale-generic/sw/bootrom.vh
Hello World

[rjfnobre]

Now it would be cool to understand what is the compilation process to generate new ELF files.

[heshamelmatary]

This port was done more than a year ago, so ABI most likely has changed.

From what I remember, the entry address here is 0x200 (this has changed on RISC-V targets like three times since then).

My advice would be:

• Install riscv32-* toolchain.
• Use bare-metal hello world app (maybe from or1k sw), and write your own linkerscript.
• Use uart 0x90000000 as a UART address and set it up same as other or1k programs.

[rjfnobre]

In what sense should I set it up as other or1k programs?

What would be the contents of the linker script for it to work with the VSCALE model in orpsoc-cores?
Can I get initialization code from any example targeting this RISCV implementation?

What about this?
https://github.com/riscv/riscv-tests/tree/master/benchmarks/common

[heshamelmatary]

The VScale port is originally ported from here [1]. I haven't tried to run any sophisticated programs/tests. There's no active contributions to this repo currently, so I'd say it's just a simple 32-bit verilog implementation. If that's what you need, you can simply write a very basic linker script and just tell it about the start address as mentioned above (or rather, just use the -T option, make sure you don't use the default linker/startuplibs). You'd also need to setup the stack, and maybe other config setup. Otherwise, you can have a look at picorv32 [2] or Rocket chip.

[1] https://github.com/ucb-bar/vscale
[2] https://github.com/cliffordwolf/picorv32

[rjfnobre]

It's that "maybe other config setup" that I would like to get hold of an example (for instance the one that generates the ELF @olofk sent me).

Where can I get the hello world bare-metal example?
I checked a repositories from OpenRISC GitHub (https://github.com/openrisc) but I could not find it.

Thanks for your help!