[GPU] Restrict memory reuse to layout-compatible buffers for oneDNN

[davidsnam-intel]

Issue:

• During GPU execution with oneDNN convolution in blocked layouts (e.g. fsv16), NaNs may appear in the output when the input feature dimension is not a multiple of the block size (typically 16) and memory reuse is enabled.
• The issue does not reproduce when memory pooling/reuse is disabled or when ocl impl for convolution is used instead of oneDNN.

Root cause:

• oneDNN primitives assume that inputs in blocked layouts are properly zero-padded in the feature tail lanes when the feature dimension is not aligned to the block size.
• However, when memory reuse is enabled, an input buffer produced by a previous primitive may contain non-zero garbage values in the feature tail lanes.
• Because oneDNN convolution reads these tail lanes implicitly, unexpected values can propagate into computation and result in NaNs.

How to fix:

• For oneDNN primitives with blocked layouts, memory reuse is restricted to buffers with layout-compatible feature dimensions.
• When the feature dimension is not aligned to the block size (e.g. not a multiple of 16 for fsv16), memory reuse is allowed only if the source and candidate buffers have matching feature sizes.
• This preserves memory reuse for compatible layouts while preventing unsafe reuse that can corrupt channel tail data

Graphs:

Tickets:

• CVS-179964

[e-ddykim]

Overall, looks good to me